Patents by Inventor Sadayoshi Hotta
Sadayoshi Hotta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9330925Abstract: A thin-film transistor includes a substrate, a gate electrode over the substrate, an insulating layer over the gate electrode, and a semiconductor layer over the insulating layer. The semiconductor layer includes a channel region, a source region, and a drain region. A source electrode is over the source region, and a drain electrode is over the drain region. The source electrode and the drain electrode each comprise Ni and a metal other than Ni. The channel region, the source region, and the drain region comprise at least one of a polycrystalline silicon that is formed by crystallizing an amorphous silicon layer by thermally diffusing the Ni in the source electrode and the drain electrode into the semiconductor layer and a microcrystalline silicon that is formed by crystallizing an amorphous silicon layer by thermally diffusing the Ni in the source electrode and the drain electrode into the semiconductor layer.Type: GrantFiled: April 8, 2010Date of Patent: May 3, 2016Assignee: JOLED INC.Inventors: Tohru Saitoh, Takaaki Ukeda, Kazunori Komori, Sadayoshi Hotta
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Patent number: 9153628Abstract: A display panel where, within at least one aperture, an inter-layer insulation layer includes a planar region having a planar surface and a protruding region having a protruding surface relative to the planar region located wherever two or more of a gate electrode, a drain electrode, a source electrode, a first power supply signal wiring, and a second power supply signal wiring intersect, and an insulation film covers at least part of the protruding region and does not cover at least part of the planar region.Type: GrantFiled: January 31, 2013Date of Patent: October 6, 2015Assignee: JOLED INC.Inventors: Takayuki Takeuchi, Sadayoshi Hotta
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Publication number: 20140367669Abstract: A display panel where, within at least one aperture, an inter-layer insulation layer includes a planar region having a planar surface and a protruding region having a protruding surface relative to the planar region located wherever two or more of a gate electrode, a drain electrode, a source electrode, a first power supply signal wiring, and a second power supply signal wiring intersect, and an insulation film covers at least part of the protruding region and does not cover at least part of the planar region.Type: ApplicationFiled: January 31, 2013Publication date: December 18, 2014Applicant: PANASONIC CORPORATIONInventors: Takayuki Takeuchi, Sadayoshi Hotta
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Patent number: 8785941Abstract: A thin-film semiconductor device includes: a first gate line; a metal line; a first gate electrode extending from the first gate line; a second gate electrode on the first gate electrode; an insulating layer provided in a crossing area where the first gate line and the metal line cross; and a second gate line formed in the same layer as the second gate electrode, and on the first gate line in other than the crossing area, wherein the metal line is on the insulating layer, the second gate line and the second gate electrode are thicker than the first gate line and the first gate electrode, and an interface between the metal line and the insulating layer is positioned above a top surface of the second gate electrode, in a cross section in a direction in which the first and second gate lines extend.Type: GrantFiled: November 19, 2012Date of Patent: July 22, 2014Assignee: Panasonic CorporationInventors: Arinobu Kanegae, Sadayoshi Hotta
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Patent number: 8716113Abstract: A semiconductor film manufacturing method includes: forming a metal layer above the substrate; forming a gate electrode in each of pixels by patterning a metal layer; forming a gate insulating firm on the gate electrode; forming an amorphous semiconductor film on the gate insulating film; and crystallizing the amorphous semiconductor film by irradiating the amorphous semiconductor film with a laser beam, and a laser irradiation width of the laser beam corresponds to n times a width of each pixel (n is an integer of 2 or above), a laser energy intensity is higher in one end portion of the laser irradiation width than in the other end portion, and in the crystallizing, the laser energy intensity of the laser beam is inverted in increments of n pixels, alternately between one of the end portions of the laser irradiation width of the laser beam and the other end portion.Type: GrantFiled: November 14, 2011Date of Patent: May 6, 2014Assignees: Panasonic Corporation, Panasonic Liquid Crystal Display Co., Ltd.Inventors: Toru Saito, Hiroshi Yoshioka, Sadayoshi Hotta
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Patent number: 8642379Abstract: A method of making a top-gate organic thin film transistor, comprising forming source and drain contacts on a substrate; oxidizing portions of the source and drain contacts; depositing an organic semiconductor layer to form a bridge between the oxidized portions of the source and drain contacts; depositing a gate insulating layer over the organic semiconductor layer; and forming a gate electrode over the gate insulating layer.Type: GrantFiled: April 3, 2008Date of Patent: February 4, 2014Assignees: Cambridge Display Technology Limited, Panasonic CorporationInventors: Sadayoshi Hotta, Jeremy Henley Burroughes, Gregory Lewis Whiting
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Patent number: 8598584Abstract: In the thin-film transistor device: the stacked thickness of either a source electrode or a drain electrode and a corresponding one of silicon layers is the same value or a value close to the same value as the stacked thickness of a first channel layer and a second channel layer; the stacked thickness of the first channel layer and the second channel layer is the same in a region between the source electrode and the drain electrode and above the source electrode and the drain electrode; the first channel layer and the second channel layer are sunken in the region between the source electrode and the drain electrode, following a shape between the source electrode and the drain electrode; and the gate electrode has one region overlapping with the source electrode and an other region overlapping with the drain electrode.Type: GrantFiled: October 17, 2011Date of Patent: December 3, 2013Assignees: Panasonic Corporation, Panasonic Liquid Crystal Display Co., Ltd.Inventors: Hisao Nagai, Sadayoshi Hotta, Genshiro Kawachi
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Patent number: 8502356Abstract: A method of forming an organic thin film transistor comprising source and drain electrodes with a channel region therebetween, a gate electrode, a dielectric layer disposed between the source and drain electrodes and the gate electrode, and an organic semiconductor disposed in at least the channel region between the source and drain electrodes, said method comprising: seeding a surface in the channel region with crystallization sites prior to deposition of the organic semiconductor; and depositing the organic semiconductor onto the seeded surface whereby the organic semiconductor crystallizes at the crystallization sites forming crystalline domains in the channel region.Type: GrantFiled: January 10, 2011Date of Patent: August 6, 2013Assignees: Cambridge Display Technology Limited, Panasonic CorporationInventors: Jonathan J. Halls, Craig Edward Murphy, Gregory Whiting, Sadayoshi Hotta
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Patent number: 8450142Abstract: An organic thin film transistor comprising: a substrate; a source electrode and a drain electrode defining a channel; a layer of insulating material disposed over the source and drain electrodes; a layer of organic semi-conductive material extending across the channel; a layer of dielectric material; and a gate electrode disposed over the layer of dielectric material.Type: GrantFiled: April 3, 2008Date of Patent: May 28, 2013Assignees: Cambridge Display Technology Limited, Panasonic CorporationInventors: Sadayoshi Hotta, Jeremy Henley Burroughes, Gregory Lewis Whiting
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Patent number: 8436355Abstract: Disclosed is a method that includes: forming a gate electrode on a substrate, then forming an insulation layer so as to completely cover the gate electrode, thereafter forming a semiconductor layer on the insulation layer, and then forming a crystallization-inducing metal layer on the semiconductor layer; removing the part of at least the crystallization-inducing metal layer that is over a channel region of the semiconductor layer; forming source and drain electrodes at a location which is over source and drain regions respectively located at opposite sides with respect to the channel region of the semiconductor layer and is above the crystallization-inducing metal layer; and heating the crystallization-inducing metal layer so as to form a silicide layer of a crystallization-inducing metal.Type: GrantFiled: November 14, 2008Date of Patent: May 7, 2013Assignee: Panasonic CorporationInventors: Takaaki Ukeda, Tohru Saitoh, Kazunori Komori, Sadayoshi Hotta
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Patent number: 8394665Abstract: A method of manufacturing an organic thin film transistor, the method comprising: depositing a source and drain electrode; forming a thin self-assembled layer of material on the source and drain electrodes, the thin self-assembled layer of material comprising a dopant moiety for chemically doping an organic semi-conductive material by accepting or donating charge and a separate attachment moiety bonded to the dopant moiety and selectively bonded to the source and drain electrodes; and depositing a solution comprising a solvent and an organic semi-conductive material in a channel region between the source and drain electrode.Type: GrantFiled: June 13, 2008Date of Patent: March 12, 2013Assignees: Cambridge Display Technology Limited, Panasonic CorporationInventors: Sadayoshi Hotta, Jonathan Halls, Gregory Whiting
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Publication number: 20120064701Abstract: A semiconductor film manufacturing method includes: forming a metal layer above the substrate; forming a gate electrode in each of pixels by patterning a metal layer; forming a gate insulating firm on the gate electrode; forming an amorphous semiconductor film on the gate insulating film; and crystallizing the amorphous semiconductor film by irradiating the amorphous semiconductor film with a laser beam, and a laser irradiation width of the laser beam corresponds to n times a width of each pixel (n is an integer of 2 or above), a laser energy intensity is higher in one end portion of the laser irradiation width than in the other end portion, and in the crystallizing, the laser energy intensity of the laser beam is inverted in increments of n pixels, alternately between one of the end portions of the laser irradiation width of the laser beam and the other end portion.Type: ApplicationFiled: November 14, 2011Publication date: March 15, 2012Applicants: PANASONIC LIQUID CRYSTAL DISPLAY CO., LTD., PANASONIC CORPORATIONInventors: Toru SAITO, Hiroshi YOSHIOKA, Sadayoshi HOTTA
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Publication number: 20120032180Abstract: In the thin-film transistor device: the stacked thickness of either a source electrode or a drain electrode and a corresponding one of silicon layers is the same value or a value close to the same value as the stacked thickness of a first channel layer and a second channel layer; the stacked thickness of the first channel layer and the second channel layer is the same in a region between the source electrode and the drain electrode and above the source electrode and the drain electrode; the first channel layer and the second channel layer are sunken in the region between the source electrode and the drain electrode, following a shape between the source electrode and the drain electrode; and the gate electrode has one region overlapping with the source electrode and an other region overlapping with the drain electrode.Type: ApplicationFiled: October 17, 2011Publication date: February 9, 2012Applicants: PANASONIC LIQUID CRYSTAL DISPLAY CO., LTD., PANASONIC CORPORATIONInventors: Hisao NAGAI, Sadayoshi HOTTA, Genshiro KAWACHI
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Patent number: 8017940Abstract: The present invention is directed to manufacturing an organic transistor with an organic semiconductor film formed by a coating method, without involving a process of forming a rib for forming the organic semiconductor film. To be more specific, the organic transistor of the present invention includes: (1) a source electrode part and a drain electrode part which are formed on a substrate; (2) rib selectively formed on part of the source electrode part and the drain electrode part; (3) an organic semiconductor film placed in the region defined by the ribs and connecting the source electrode part and the drain electrode part; and (4) a gate electrode formed on the organic semiconductor film through a gate insulating film. The organic transistor of the present invention is characterized in that there is a gap between the rib formed on the source electrode part and the rib formed on the drain electrode part.Type: GrantFiled: May 23, 2008Date of Patent: September 13, 2011Assignee: Panasonic CorporationInventors: Shuhei Nakatani, Sadayoshi Hotta, Hidehiro Yoshida
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Publication number: 20110101323Abstract: A method of forming an organic thin film transistor comprising source and drain electrodes with a channel region therebetween, a gate electrode, a dielectric layer disposed between the source and drain electrodes and the gate electrode, and an organic semiconductor disposed in at least the channel region between the source and drain electrodes, said method comprising: seeding a surface in the channel region with crystallization sites prior to deposition of the organic semiconductor; and depositing the organic semiconductor onto the seeded surface whereby the organic semiconductor crystallizes at the crystallization sites forming crystalline domains in the channel region.Type: ApplicationFiled: January 10, 2011Publication date: May 5, 2011Applicants: CAMBRIDGE DISPLAY TECHNOLOGY LIMITED, PANASONIC CORPORATIONInventors: Jonathan J. Halls, Craig E. Murphy, Gregory Whiting, Sadayoshi Hotta
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Patent number: 7867813Abstract: A method of forming an organic thin film transistor comprising source and drain electrodes with a channel region therebetween, a gate electrode, a dielectric layer disposed between the source and drain electrodes and the gate electrode, and an organic semiconductor disposed in at least the channel region between the source and drain electrodes, said method comprising: seeding a surface in the channel region with crystallization sites prior to deposition of the organic semiconductor; and depositing the organic semiconductor onto the seeded surface whereby the organic semiconductor crystallizes at the crystallization sites forming crystalline domains in the channel region.Type: GrantFiled: June 20, 2008Date of Patent: January 11, 2011Assignees: Cambridge Display Technology Limited, Panasonic CorporationInventors: Jonathan J. Halls, Craig E. Murphy, Gregory Whiting, Sadayoshi Hotta
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Publication number: 20100320467Abstract: Disclosed is a method that includes: forming a gate electrode on a substrate, then forming an insulation layer so as to completely cover the gate electrode, thereafter forming a semiconductor layer on the insulation layer, and then forming a crystallization-inducing metal layer on the semiconductor layer; removing the part of at least the crystallization-inducing metal layer that is over a channel region of the semiconductor layer; forming source and drain electrodes at a location which is over source and drain regions respectively located at opposite sides with respect to the channel region of the semiconductor layer and is above the crystallization-inducing metal layer; and heating the crystallization-inducing metal layer so as to form a silicide layer of a crystallization-inducing metal.Type: ApplicationFiled: November 14, 2008Publication date: December 23, 2010Applicant: PANASONIC CORPORATIONInventors: Takaaki Ukeda, Tohru Saitoh, Kazunori Komori, Sadayoshi Hotta
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Publication number: 20100203663Abstract: A method of manufacturing an organic thin film transistor, the method comprising: depositing a source and drain electrode; forming a thin self-assembled layer of material on the source and drain electrodes, the thin self-assembled layer of material comprising a dopant moiety for chemically doping an organic semi-conductive material by accepting or donating charge and a separate attachment moiety bonded to the dopant moiety and selectively bonded to the source and drain electrodes; and depositing a solution comprising a solvent and an organic semi-conductive material in a channel region between the source and drain electrode.Type: ApplicationFiled: June 13, 2008Publication date: August 12, 2010Applicants: CAMBRIDGE DISPLAY TECHNOLOGY LIMITED, PANASONIC CORPORATIONInventors: Sadayoshi Hotta, Jonathan Halls, Gregory Whiting
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Publication number: 20100194719Abstract: A thin-film transistor includes a substrate, a gate electrode over the substrate, an insulating layer over the gate electrode, and a semiconductor layer over the insulating layer. The semiconductor layer includes a channel region, a source region, and a drain region. A source electrode is over the source region, and a drain electrode is over the drain region. The source electrode and the drain electrode each comprise Ni and a metal other than Ni. The channel region, the source region, and the drain region comprise at least one of a polycrystalline silicon that is formed by crystallizing an amorphous silicon layer by thermally diffusing the Ni in the source electrode and the drain electrode into the semiconductor layer and a microcrystalline silicon that is formed by crystallizing an amorphous silicon layer by thermally diffusing the Ni in the source electrode and the drain electrode into the semiconductor layer.Type: ApplicationFiled: April 8, 2010Publication date: August 5, 2010Applicant: PANASONIC CORPORATIONInventors: Tohru SAITOH, Takaaki UKEDA, Kazunori KOMORI, Sadayoshi HOTTA
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Publication number: 20100084638Abstract: A method of making a top-gate organic thin film transistor, comprising forming source and drain contacts on a substrate; oxidizing portions of the source and drain contacts; depositing an organic semiconductor layer to form a bridge between the oxidized portions of the source and drain contacts; depositing a gate insulating layer over the organic semiconductor layer; and forming a gate electrode over the gate insulating layer.Type: ApplicationFiled: April 3, 2008Publication date: April 8, 2010Applicants: Cambridge Display Technology Limited, Panasonic CorporationInventors: Sadayoshi Hotta, Jeremy Henley Burroughes, Gregory Lewis Whiting