Abstract: A semiconductor memory device comprising a first Electrically Erasable Programmable Read Only Memory (EEPROM) cell array, a first row decoder, a first column decoder, two second EEPROM arrays each having a storage area equal in capacity to the specified storage area defined in the first EEPROM array, a second row decoder, a second column decoder, and a majority logic circuit. The first row decoder and the first column decoder access one of the memory cells of the first EEPROM array. The second row decoder and the second column decoder access one of the memory cells of either the second EEPROM array when one of the memory cells of first EEPROM array is accessed. The majority logic circuit carries out a majority logic operation on the data items read from the accessed memory cell of the first EEPROM array and the data items read from the accessed memory cells of the second EEPROM arrays, thereby to determine which data item is to be read out to an external device.

Abstract: In a non-volatile semiconductor memory of this invention, a memory cell array constituted by a plurality of memory cells is divided into a plurlaity of blocks, and erase lines which are common to the respective blocks and independent from each other are arranged. In the data write mode, a predetermined voltage is applied to only the erase line connected to a selected one of the blocks.

Abstract: In an electrically erasable non-volatile semiconductor memory device, a plurality of non-volatile semiconductor memory cells are arranged in a matrix form and are connected to corresponding ones of row and column lines. In a data writing mode, a first voltage Vp at is applied to the column lines so that the drains of the memory cells are maintained at a drain potential, and a second voltage is applied to the row lines so that a sum level of the drain potential and the threshold voltage of the memory cell is not smaller than the floating gate potential of the memory cell.

Abstract: In a nonvolatile semiconductor memory, each of a plurality of memory cells arranged in the form of a matrix includes a p-type semiconductor region, an n-type source connected to the ground potential, an n-type drain formed in a longitudinal direction with respect to the source, a channel region located between the source and the drain, a control gate transversely extending and formed above the channel region, intervening a first insulating film, a floating gate formed in the first insulating film above the channel region, and an erase gate formed in the first insulating film so as to spatially overlap one end of the floating gate. The memory further includes an erase line extending in the longitudinal direction, formed in the first insulating film and connected to the erase gate, and a data line, connected to the drain. First and second memory cells of the plurality of memory cells are arranged to be adjacent to one another in the transverse direction to constitute a first memory cell pair.