Abstract: The present disclosure relates to an event-driven integrated circuit that includes a sensor, an interface system, and a processor. The interface module includes a copy module, a merge module, a sub-sampling module, an ROI module, and an event routing module. The modules constitute a programmable daisy chain. The sensor, interface system and processor are coupled to a single chip through an interposer or manufactured in a same die by different manufacturing processes. In contrast to prior art, the event-driven integrated circuit with lower chip occupied area and manufacturing cost can eliminate the signal loss and noise interference, and achieve high-speed signal processing, solving the technical problems of larger chip area and weak signal processing ability. The interface system enriches the functions and configurability of the interface system, and provides various advantages in power consumption, function, and speed for subsequent processing.

Abstract: The invention relates to an event-driven spiking convolutional neural network, comprising a plurality of layers, wherein each layer comprises a kernel module (110) configured to store and to process in an event-driven fashion kernel values of at least one convolution kernel (410); a neuron module (120) configured to store and to update in an event-driven fashion neuron states of neurons of the spiking neural network (1), and to output spike events (150) generated from updated neurons (420); a memory mapper (130) configured to determine neurons (420) to which an incoming spike event (140) from a source layer projects by means of a convolution with at least one convolution kernel (410) and wherein neuron states of said determined neurons (420) are to be updated with applicable kernel values of the at least one convolution kernel (410), wherein the memory mapper (130) is configured to process incoming spike events in an event-driven fashion.

Abstract: A spike sent from a first artificial neuron in a spiking neural network (SNN) to a second artificial neuron in the SNN is identified, with the spike sent over a particular artificial synapse in the SNN. The membrane potential of the second artificial neuron at a particular time step, corresponding to sending of the spike, is compared to a threshold potential, where the threshold potential is set lower than a firing potential of the second artificial neuron. A change to the synaptic weight of the particular artificial synapse is determined based on the spike, where the synaptic weight is to be decreased if the membrane potential of the second artificial neuron is lower than the threshold potential at the particular time step and the synaptic weight is to be increased if the membrane potential of the second artificial neuron is higher than the threshold potential at the particular time step.

Abstract: Technologies for memory management of a neural network include a compute device to read a memory of the compute device to access connectivity data associated with a neuron of the neural network, determine a memory address at which weights corresponding with the one or more network connections are stored, and access the corresponding weights from a memory location corresponding with the memory address. The connectivity data is indicative of one or more network connections from the neuron.

Abstract: A spike sent from a first artificial neuron in a spiking neural network (SNN) to a second artificial neuron in the SNN is identified, with the spike sent over a particular artificial synapse in the SNN. The membrane potential of the second artificial neuron at a particular time step, corresponding to sending of the spike, is compared to a threshold potential, where the threshold potential is set lower than a firing potential of the second artificial neuron. A change to the synaptic weight of the particular artificial synapse is determined based on the spike, where the synaptic weight is to be decreased if the membrane potential of the second artificial neuron is lower than the threshold potential at the particular time step and the synaptic weight is to be increased if the membrane potential of the second artificial neuron is higher than the threshold potential at the particular time step.

Abstract: Embodiments include apparatuses, systems, and methods including a memory apparatus including a plurality of bit cells, wherein each of the plurality of bit cells correspond to a respective weight value and include a switch device that has a magnetic tunnel junction (MTJ) or other suitable resistive memory element to produce stochastic switching. In embodiments, the switch device may produce a switching output according to a stochastic switching probability of the switch device. In embodiments, a bit line or a source line passes a current across the MTJ for a switching time associated with the stochastic switching probability to produce the switching output which enables a determination of whether the respective weight value is to be updated. Other embodiments may also be described and claimed.

Abstract: Embodiments include apparatuses, systems, and methods including a memory apparatus including a plurality of bit cells, wherein each of the plurality of bit cells correspond to a respective weight value and include a switch device that has a magnetic tunnel junction (MTJ) or other suitable resistive memory element to produce stochastic switching. In embodiments, the switch device may produce a switching output according to a stochastic switching probability of the switch device. In embodiments, a bit line or a source line passes a current across the MTJ for a switching time associated with the stochastic switching probability to produce the switching output which enables a determination of whether the respective weight value is to be updated. Other embodiments may also be described and claimed.

Abstract: Technologies for memory management of a neural network include a compute device to read a memory of the compute device to access connectivity data associated with a neuron of the neural network, determine a memory address at which weights corresponding with the one or more network connections are stored, and access the corresponding weights from a memory location corresponding with the memory address. The connectivity data is indicative of one or more network connections from the neuron.

Abstract: Embodiments include apparatuses, systems, and methods including a memory apparatus including a plurality of bit cells, wherein each of the plurality of bit cells correspond to a respective weight value and include a switch device that has a magnetic tunnel junction (MTJ) or other suitable resistive memory element to produce stochastic switching. In embodiments, the switch device may produce a switching output according to a stochastic switching probability of the switch device. In embodiments, a bit line or a source line passes a current across the MTJ for a switching time associated with the stochastic switching probability to produce the switching output which enables a determination of whether the respective weight value is to be updated. Other embodiments may also be described and claimed.