Abstract: An receiver receives, amplifies, filters, and downconverts an RF signal to obtain an FM signal. The FM signal is then limited by a limiter and sampled by an ADC. The FM samples from the ADC are provided to an edge detector which detects transitions in the FM samples. The transitions correspond to zero crossings in the FM signal. The time period between the zero crossings, or the cycle width, is measured with a counter to determine the instantaneous frequency f.sub.c of the FM signal. The demodulated output is proportional to the instantaneous frequency which can be determined from the measured cycle periods as f.sub.c =1/2T.sub.c, f.sub.c .apprxeq.-.alpha.T.sub.c, or f.sub.c .varies.T.sub.c, where T.sub.c is the measured cycle period, and .alpha. is a constant based on the slope of 1/2T.sub.c,avg, where T.sub.c,avg is the average cycle period. The sample rate of the demodulated output can be reduced, through resampling, to minimize power consumption in the subsequent signal processing blocks.

Abstract: A phase lock loop wherein the reference clock is divided by a variable divider which is capable of dividing the reference clock by a divider ratio of 2, 3, 4, . . . or M depending on the value of a control signal. The control signal is generated from a divider controller in response to a controller input. The noise shaping characteristics of the divider controller results in dithering of the variable divider ratios such that the average frequency of the divided reference clock is at the desired comparison frequency but the quantization noise from the fractional divide is pushed from low frequency to high frequency where it is more easily filtered. The noise shaper can be implemented with many bits of resolution to allow for a wide frequency control range and high frequency accuracy. A dither circuit to prevent limit cycling at the output of the noise shaper.