Abstract: A method of making and testing a system on chip (SOC) comprises providing an integrated system test (IST) module in each one of a plurality of SOC components. At least one of the SOC components communicates with an external interface and at least one other of the SOC components. The method includes receiving test configuration data, transmitting test result data, and transmitting and receiving application data via the external interface. The method includes using at least one of the IST modules to receive the test configuration data and configure the IST modules to test the plurality of SOC components.

Abstract: A system on chip (SOC), comprises an external interface that receives test configuration data, transmits test result data, and that transmits and receives application data. A plurality of SOC components, each including an integrated system test (IST) module, wherein at least one of the SOC components includes a controller that communicates with the external interface. At least one of the plurality of SOC components communicates with the controller. At least one of the IST modules is a master IST module that receives the test configuration data and configures the IST modules for testing the plurality of SOC components.

Abstract: A hard disk drive system comprises N hard disk drive means for performing hard disk drive functions and is connected in a daisy chain, wherein N is greater than one. The system includes integrated system test (IST) means for testing and that is integrated with a first one of the N hard disk drive means and includes pattern generating means for generating test pattern data and pattern monitoring means for receiving a returned test pattern. The pattern generating means generates test pattern data that is routed from the first one of the N hard disk drive means serially through the remaining ones of the N hard disk drive means and back to the first one of the N hard disk drive means. The pattern monitoring means generates test result data based on returned test data returned to the first one of the N hard disk drive means.

Abstract: A hard disk drive system includes an external interface that receives test configuration data, that transmits test result data, and that transmits and receives application data. The hard disk drive system includes a system on chip (SOC) that includes a controller and a read/write channel that communicates with the controller and that includes an integrated system test (IST) module that communicates with the external interface. A memory module communicates with the SOC and includes memory and an IST module. The hard disk drive system includes a spindle/voice coil motor driver module that includes an IST module. At least one of the IST modules is a master IST module that receives the test configuration data and that configures the IST modules for testing at least one of the controller, the read/write channel, and the memory module.

Abstract: A system comprises a printed circuit board (PCB). A system on chip (SOC) mounted on the PCB includes a controller that communicates with an external interface that receives test configuration data, transmits test result data, and transmits and receives application data. At least one chip mounted to the PCB, wherein the SOC comprises an SOC component that includes an integrated system test (IST) module. At least one chip comprises a chip component that includes an integrated system test (IST) module. At least one of the SOC component and the chip component, communicates with the controller. At least one of the IST modules is a master IST module that receives the test configuration data and configures the IST modules for testing at least one of the SOC component and the chip component.

Abstract: A hard disk controller having a latency-independent interface comprises a data gate circuit that transmits a data gate signal. A data circuit transmits or receives data under control of the data gate signal. A media gate circuit transmits a media gate signal. A mode selection circuit transmits mode selection information under control of the media gate signal, wherein said data gate signal controls the transfer of data between the hard disk controller and a read/write channel in accordance with the media gate signal.

Abstract: A memory circuit includes a memory interface and a first memory that receives a first write address that is associated with first data from said memory interface. A second memory stores addresses of defective memory locations found in said first memory, receives said first write address from said memory interface, compares said first write address to said addresses stored in said memory, and, if a matching address is found, writes said first data to said second memory.

Abstract: A latency-independent interface between hardware components, such as a hard disk controller (HDC) and a read/write (R/W) channel or a read channel (RDC) supports high read and write latencies of greater than one sector. Such an interface also supports a split sector format and multiple mark format. In addition to read and write clock signals, the interface comprises a data gate signal that controls the transfer of data between the the HDC and R/W channel, and a media gate signal that controls transfer of mode selection information from the HDC to the R/W channel and also controls the transfer of data between the R/W channel and a disk. The media gate signal replaces the conventional read and write gate control signals. A buffer attention signal is also provided.

Abstract: A latency-independent interface between hardware components, such as a hard disk controller (HDC) and a read/write (R/W) channel or a read channel (RDC) supports high read and write latencies of greater than one sector. Such an interface also supports a split sector format and multiple mark format. In addition to read and write clock signals, the interface comprises a data gate signal that controls the transfer of data between the the HDC and R/W channel, and a media gate signal that controls transfer of mode selection information from the HDC to the R/W channel and also controls the transfer of data between the R/W channel and a disk. The media. gate signal replaces the conventional read and write gate control signals. A buffer attention signal is also provided.

Abstract: A memory architecture for a disk drive system in which (Synchronous Random Access Memory) SRAM and Dynamic Random Access Memory (DRAM) functions are provided on separate integrated circuits, and an interface protocol for transmitting information between these two memory components are provided to improve performance of the system, as well as reduce pin count and cost. The SRAM is an “on-board” memory component, meaning that it is embodied on an integrated circuit that also includes a hard disk controller (HDC) and other disk drive components, while the DRAM is located on a separate integrated circuit externally, i.e., “off-board,” of the integrated circuit containing the SRAM. The SRAM includes a random access (RA) block that provides all RA functions, while the DRAM includes a direct memory access (DMA) block that provides all DMA functions.

Abstract: A memory architecture for a disk drive system in which (Synchronous Random Access Memory) SRAM and Dynamic Random Access Memory (DRAM) functions are provided on separate integrated circuits, and an interface protocol for transmitting information between these two memory components are provided to improve performance of the system, as well as reduce pin count and cost. The SRAM is an “on-board” memory component, meaning that it is embodied on an integrated circuit that also includes a hard disk controller (HDC) and other disk drive components, while the DRAM is located on a separate integrated circuit externally, i.e., “off-board,” of the integrated circuit containing the SRAM. The SRAM includes a random access (RA) block that provides all RA functions, while the DRAM includes a direct memory access (DMA) block that provides all DMA functions.

Abstract: An interface testing circuit and method for testing an interface between two or more separate hardware components provides interface testing capability without requiring complex and expensive synchronized mixed signal testing between the hardware components. The interface testing circuit includes two or more sub-circuits, each of which is adapted to selectively route either a test signal from a test input/output pad to a hardware component or route an output signal from another hardware component to the test pad. Multiple testing modes are used to fully test the interface.