Abstract: Phononic crystal wave structures and methods of making same are discussed in this application. According to some embodiments, an acoustic structure can generally comprise a phononic crystal slab configured as a micro/nano-acoustic wave medium. The phononic crystal slab can define an exterior surface that bounds an interior volume, and the phononic crystal slab can be sized and shaped to contain acoustic waves within the interior volume of the phononic crystal slab. The phononic crystal slab can comprise at least one defect portion. The defect portion can affect periodicity characteristics of the phononic crystal slab. The defect portion can be shaped and arranged to enable confinement and manipulation of acoustic waves through the defect portion(s) of phononic crystal slab. Other aspects, features, and embodiments are also claimed and described.

Abstract: Illustrative embodiments of a power amplifier are disclosed which include a plurality of amplifier cells, each having an input and an output. The plurality of amplifier cells are formed on a semiconductor substrate such that the outputs of the plurality of amplifier cells are electrically coupled in series. Each of the plurality of amplifier cells may comprise a first transistor that is electrically insulated from the semiconductor substrate and a first feedback resistor configured to dynamically bias the first transistor.

Abstract: Phononic crystal wave structures and methods of making same are discussed in this application. According to some embodiments, an acoustic structure can generally comprise a phononic crystal slab configured as a micro/nano-acoustic wave medium. The phononic crystal slab can define an exterior surface that bounds an interior volume, and the phononic crystal slab can be sized and shaped to contain acoustic waves within the interior volume of the phononic crystal slab. The phononic crystal slab can comprise at least one defect portion. The defect portion can affect periodicity characteristics of the phononic crystal slab. The defect portion can be shaped and arranged to enable confinement and manipulation of acoustic waves through the defect portion(s) of phononic crystal slab. Other aspects, features, and embodiments are also claimed and described.

Abstract: A method for etching a substrate is described wherein a substrate is positioned in a solution of solvent and the substrate is exposed to excitation energy. The method may be applied to the production of thermocouple devices wherein the substrate is poly-ethylene-terephthalate.

Abstract: A polymer-based, self-aligned wafer-level heterogeneous integration system, SAWLIT, for integrating semiconductor integrated circuit (IC) chips to a substrate is presented. The system includes a method including preparing a substrate, flipping the substrate onto a polymer-based flat surface and securing the substrate to the flat surface, mounting semiconductor chips into the prepared substrate, integrating the chips to the substrate with another polymer-based material, and removing the resulting multi-chip module from the flat surface. The chips may then be connected with each other and regions off the multi-chip module with metal interconnect processing technology. A multi-chip module prepared by the polymer-based, self-aligned heterogeneous integration system including semiconductor chips mounted in a prepared substrate. The chips may be connected to the substrate by a polymer-based integrating material.

Abstract: A polymer-based, self-aligned wafer-level heterogeneous integration system, SA WLIT, for integrating semiconductor integrated circuit (IC) chips to a substrate is presented. The system includes a method including preparing a substrate, flipping the substrate onto a polymer-based flat surface and securing the substrate to the flat surface, mounting semiconductor chips into the prepared substrate, integrating the chips to the substrate with another polymer-based material, and removing the resulting multi-chip module from the flat surface. The chips may then be connected with each other and regions off the multi-chip module with metal interconnect processing technology. A multi-chip module prepared by the polymer-based, self-aligned heterogeneous integration system including semiconductor chips mounted in a prepared substrate. The chips may be connected to the substrate by a polymer-based integrating material.

Abstract: A polymer-based, self-aligned wafer-level heterogeneous integration system, SA WLIT, for integrating semiconductor integrated circuit (IC) chips to a substrate is presented. The system includes a method including preparing a substrate, flipping the substrate onto a polymer-based flat surface and securing the substrate to the flat surface, mounting semiconductor chips into the prepared substrate, integrating the chips to the substrate with another polymer-based material, and removing the resulting multi-chip module from the flat surface. The chips may then be connected with each other and regions off the multi-chip module with metal interconnect processing technology. A multi-chip module prepared by the polymer-based, self-aligned heterogeneous integration system including semiconductor chips mounted in a prepared substrate. The chips may be connected to the substrate by a polymer-based integrating material.

Abstract: A stressed metal technology may fabricate high-Q, three-dimensional microelectronic inductors and transformers. The fabrication method may allow the production of inductors and transformers on high-resistivity silicon substrate and with metal deposition of Au and Cr that is fully compatible with semiconductor fabrication technologies. The produced inductors and transformers exhibit Q factors>60 at frequencies of 3 to 7 GHz. High efficiency, high-Q transformers with coupling factors 0.6<k<0.9 may be created with very high self-resonance frequencies.

Abstract: A stressed metal technology may fabricate high-Q, three-dimensional microelectronic inductors and transformers. The fabrication method may allow the production of inductors and transformers on high-resistivity silicon substrate and with metal deposition of Au and Cr that is fully compatible with semiconductor fabrication technologies. The produced inductors and transformers exhibit Q factors>60 at frequencies of 3 to 7 GHz. High efficiency, high-Q transformers with coupling factors 0.6<k<0.

Abstract: A method for etching a substrate is described wherein a substrate is positioned in a solution of solvent and the substrate is exposed to excitation energy. The method may be applied to the production of thermocouple devices wherein the substrate is poly-ethylene-terephthalate.