Patents by Inventor Saeed S. Shojaie
Saeed S. Shojaie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11700696Abstract: Embodiments are generally directed to a buried electrical debug access port. An embodiment of an apparatus includes a substrate or printed circuit board; one or more electronic components coupled with the substrate or printed circuit board; one or more electrical access ports coupled with the substrate or printed circuit board, each electrical access port including electrically conductive material; and an encapsulant material, the encapsulant material encapsulating the one or more access ports, wherein the one or more access ports are electrically connected to one or more circuits of the apparatus to provide debugging access to the apparatus.Type: GrantFiled: June 3, 2021Date of Patent: July 11, 2023Assignee: Intel CorporationInventors: Florence R. Neumann, Bilal Khalaf, Saeed S. Shojaie
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Publication number: 20210298183Abstract: Embodiments are generally directed to a buried electrical debug access port. An embodiment of an apparatus includes a substrate or printed circuit board; one or more electronic components coupled with the substrate or printed circuit board; one or more electrical access ports coupled with the substrate or printed circuit board, each electrical access port including electrically conductive material; and an encapsulant material, the encapsulant material encapsulating the one or more access ports, wherein the one or more access ports are electrically connected to one or more circuits of the apparatus to provide debugging access to the apparatus.Type: ApplicationFiled: June 3, 2021Publication date: September 23, 2021Inventors: Florence R. PON, Bilal KHALAF, Saeed S. SHOJAIE
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Patent number: 11064612Abstract: Embodiments are generally directed to a buried electrical debug access port. An embodiment of an apparatus includes a substrate or printed circuit board; one or more electronic components coupled with the substrate or printed circuit board; one or more electrical access ports coupled with the substrate or printed circuit board, each electrical access port including electrically conductive material; and an encapsulant material, the encapsulant material encapsulating the one or more access ports, wherein the one or more access ports are electrically connected to one or more circuits of the apparatus to provide debugging access to the apparatus.Type: GrantFiled: April 1, 2016Date of Patent: July 13, 2021Assignee: Intel CorporationInventors: Florence R. Pon, Bilal Khalaf, Saeed S. Shojaie
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Publication number: 20190131278Abstract: Apparatuses, methods and storage medium associated with integrated packaging for a stack of semiconductor dice of different sizes are disclosed herein. In embodiments, an apparatus including dice of different sizes may include a first die having a first side and a second side opposite the first side and a second smaller die having a first side and a second side opposite the first side the second side. The second side of the first die may be smaller than the first side of the second die and may be coupled thereto such that a portion of the first side of the second die is exposed. The apparatus may include wires coupled with and extending from the portion of the first side of the second die through a casing to a redistribution layer coupled with a side of the casing, to electrically couple the dice. Other embodiments may be disclosed and/or claimed.Type: ApplicationFiled: December 20, 2018Publication date: May 2, 2019Inventor: Saeed S. Shojaie
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Patent number: 10204884Abstract: Apparatuses, methods and storage medium associated with integrated packaging for a stack of semiconductor dice of different sizes are disclosed herein. In embodiments, an apparatus including dice of different sizes may include a first die having a first side and a second side opposite the first side and a second smaller die having a first side and a second side opposite the first side the second side. The second side of the first die may be smaller than the first side of the second die and may be coupled thereto such that a portion of the first side of the second die is exposed. The apparatus may include wires coupled with and extending from the portion of the first side of the second die through a casing to a redistribution layer coupled with a side of the casing, to electrically couple the dice. Other embodiments may be disclosed and/or claimed.Type: GrantFiled: June 29, 2016Date of Patent: February 12, 2019Assignee: Intel CorporationInventor: Saeed S. Shojaie
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Patent number: 10090261Abstract: A microelectronic package may be fabricated with debug access ports formed either at a side or at a bottom of the microelectronic package. In one embodiment, the debug access ports may be formed within an encapsulation material proximate the microelectronic package side. In another embodiment, the debug access ports may be formed in a microelectronic interposer of the microelectronic package proximate the microelectronic package side. In a further embodiment, the debug access ports may be formed at the microelectronic package bottom and may include a solder contact.Type: GrantFiled: March 28, 2017Date of Patent: October 2, 2018Assignee: Intel CorporationInventors: Florence R. Pon, Bilal Khalaf, Saeed S. Shojaie
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Patent number: 9936582Abstract: Embodiments of integrated circuit (IC) assemblies and related techniques are disclosed herein. For example, in some embodiments, an IC assembly may include a first printed circuit board (PCB) having a first face and an opposing second face; a die electrically coupled to the first face of the first PCB; a second PCB having a first face and an opposing second face, wherein the second face of the second PCB is coupled to the first face of the first PCB via one or more solder joints; and a molding compound. The molding compound may be in contact with the first face of the first PCB and the second face of the second PCB. Other embodiments may be disclosed and/or claimed.Type: GrantFiled: April 30, 2014Date of Patent: April 3, 2018Assignee: INTEL CORPORATIONInventors: Junfeng Zhao, Saeed S. Shojaie, Cheng Yang
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Publication number: 20180090467Abstract: Embodiments herein relate to thermal coupling using through mold vias (TMV). Embodiments may include a substrate having a first side and a second side opposite the first side, a processor having a first side and the second side, the first side of the processor coupled to the first side of the substrate, one or more solder balls where the first side of the one or more solder balls are thermally coupled to the second side of the processor and where the solder balls are embedded in one or more TMVs in a molding extending from a first side of the molding to a second side of the molding opposite the first side of the molding. Other embodiments may be described and/or claimed.Type: ApplicationFiled: September 27, 2016Publication date: March 29, 2018Inventors: Hyoung II Kim, Saeed S. Shojaie
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Publication number: 20180005990Abstract: Apparatuses, methods and storage medium associated with integrated packaging for a stack of semiconductor dice of different sizes are disclosed herein. In embodiments, an apparatus including dice of different sizes may include a first die having a first side and a second side opposite the first side and a second smaller die having a first side and a second side opposite the first side the second side. The second side of the first die may be smaller than the first side of the second die and may be coupled thereto such that a portion of the first side of the second die is exposed. The apparatus may include wires coupled with and extending from the portion of the first side of the second die through a casing to a redistribution layer coupled with a side of the casing, to electrically couple the dice. Other embodiments may be disclosed and/or claimed.Type: ApplicationFiled: June 29, 2016Publication date: January 4, 2018Inventor: Saeed S. Shojaie
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Publication number: 20170285097Abstract: Embodiments are generally directed to a buried electrical debug access port. An embodiment of an apparatus includes a substrate or printed circuit board; one or more electronic components coupled with the substrate or printed circuit board; one or more electrical access ports coupled with the substrate or printed circuit board, each electrical access port including electrically conductive material; and an encapsulant material, the encapsulant material encapsulating the one or more access ports, wherein the one or more access ports are electrically connected to one or more circuits of the apparatus to provide debugging access to the apparatus.Type: ApplicationFiled: April 1, 2016Publication date: October 5, 2017Inventors: Florence R. PON, Bilal KHALAF, Saeed S. SHOJAIE
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Publication number: 20170200685Abstract: A microelectronic package may be fabricated with debug access ports formed either at a side or at a bottom of the microelectronic package. In one embodiment, the debug access ports may be formed within an encapsulation material proximate the microelectronic package side. In another embodiment, the debug access ports may be formed in a microelectronic interposer of the microelectronic package proximate the microelectronic package side. In a further embodiment, the debug access ports may be formed at the microelectronic package bottom and may include a solder contact.Type: ApplicationFiled: March 28, 2017Publication date: July 13, 2017Applicant: INTEL CORPORATIONInventors: Florence R. Pon, Bilal Khalaf, Saeed S. Shojaie
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Patent number: 9646952Abstract: A microelectronic package may be fabricated with debug access ports formed either at a side or at a bottom of the microelectronic package. In one embodiment, the debug access ports may be formed within an encapsulation material proximate the microelectronic package side. In another embodiment, the debug access ports may be formed in a microelectronic interposer of the microelectronic package proximate the microelectronic package side. In a further embodiment, the debug access ports may be formed at the microelectronic package bottom and may include a solder contact.Type: GrantFiled: September 17, 2015Date of Patent: May 9, 2017Assignee: Intel CorporationInventors: Florence R. Pon, Bilal Khalaf, Saeed S. Shojaie
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Publication number: 20170084573Abstract: A microelectronic package may be fabricated with debug access ports formed either at a side or at a bottom of the microelectronic package. In one embodiment, the debug access ports may be formed within an encapsulation material proximate the microelectronic package side. In another embodiment, the debug access ports may be formed in a microelectronic interposer of the microelectronic package proximate the microelectronic package side. In a further embodiment, the debug access ports may be formed at the microelectronic package bottom and may include a solder contact.Type: ApplicationFiled: September 17, 2015Publication date: March 23, 2017Applicant: INTEL CORPORATIONInventors: Florence R. Pon, Bilal Khalaf, Saeed S. Shojaie
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Publication number: 20150359100Abstract: Embodiments of integrated circuit (IC) assemblies and related techniques are disclosed herein. For example, in some embodiments, an IC assembly may include a first printed circuit board (PCB) having a first face and an opposing second face; a die electrically coupled to the first face of the first PCB; a second PCB having a first face and an opposing second face, wherein the second face of the second PCB is coupled to the first face of the first PCB via one or more solder joints; and a molding compound. The molding compound may be in contact with the first face of the first PCB and the second face of the second PCB. Other embodiments may be disclosed and/or claimed.Type: ApplicationFiled: April 30, 2014Publication date: December 10, 2015Inventors: Junfeng Zhao, Saeed S. Shojaie, Cheng Yang