Patents by Inventor Saeid Moshkelani

Saeid Moshkelani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Simulation tool input file generator for interface circuitry
    Patent number: 6292766
    Abstract: The present invention is a simulation tool input file generator implemented in a computer system that permits a designer to efficiently and effectively create and modify electrical circuit simulation tool input files. The simulation tool input file generator permits a user to conveniently enter high level circuit description information in user friendly formats such as an easy to use GUI. Based upon the information provided by a user, the present invention assembles data including circuit description files stored in a memory and produces a detailed simulation tool input files.
    Type: Grant
    Filed: December 18, 1998
    Date of Patent: September 18, 2001
    Assignee: VLSI Technology, Inc.
    Inventors: Derwin Mattos, Henry Jen, Saeid Moshkelani