Abstract: A gas blocking cable includes cabled wires, where each wire includes cabled conductors having interstitial areas there between. An insulation material circumferentially surrounds the cabled conductors and a conductor filling material is positioned within the interstitial areas between conductors. A first shield circumferentially surrounds the twisted wires and a high-temperature filler, thereby separating a drain wire. A second shield circumferentially surrounds the cabled wires and the drain wire so that a cable is formed with areas between the first shield and the second shield. A wire filling material is positioned within the areas between the wires and the shields. Each of the conductor filling material and wire filling material is inert, non-flammable and able to withstand a temperature of at least approximately 200° C.

Abstract: This disclosure provides systems, methods and apparatus related to biometric authentication of a user of an electronic device. An electronic display has a display cover glass with a front surface that includes a viewing area, and a fingerprint reading area within the viewing area. At least one photosensing element is configured to detect received scattered light, the received scattered light resulting from interaction of light with an object in at least partial optical contact with the front surface within the fingerprint reading area and to output, to a processor, fingerprint image data.

Abstract: A gas blocking cable includes cabled wires, where each wire includes cabled conductors having interstitial areas there between. An insulation material circumferentially surrounds the cabled conductors and a conductor filling material is positioned within the interstitial areas between conductors. A first shield circumferentially surrounds the twisted wires and a high-temperature filler, thereby separating a drain wire. A second shield circumferentially surrounds the cabled wires and the drain wire so that a cable is formed with areas between the first shield and the second shield. A wire filling material is positioned within the areas between the wires and the shields. Each of the conductor filling material and wire filling material is inert, non-flammable and able to withstand a temperature of at least approximately 200° C.

Abstract: A receiver includes a turbo decoder, and a depuncture module configured to enable the turbo decoder to selectively operate at a symmetric code rate and an asymmetric code rate.

Abstract: A system and method are provided for parallel path turbo decoding in a portable wireless communications user terminal (UT). The method accepts a coded stream having a first order of information packets, and demultiplexes the coded stream into first coded and second coded information streams. The first coded stream is turbo decoded, generating a first decoded information stream. Likewise, the second coded stream is decoded to generate a second decoded information stream, asynchronously with respect to the first decoded stream. Then, the first and second decoded streams are combined into a combined stream having the first order of decoded information packets. The first and second decoded streams are combined by parallel buffering the first and second decoded streams, generating parallel-buffered decoded streams. Then, the parallel-buffered decoded streams are multiplexed to create a combined stream, which is stored in an output buffer.

Abstract: A microprocessor system having an interrupt controller is provided for use in a mobile communications device. Peripheral processing units generate interrupt requests for sending to the microprocessor. The microprocessor has components for responding to interrupt requests by interrupting current processing and performing an interrupt service routine associated with the interrupt request. The interrupt controller receives interrupt requests directed to the microprocessor from the peripheral processing units and for prioritizes the interrupt requests on behalf of the microprocessor. By providing an interrupt controller for prioritizing interrupt requests on behalf of the microprocessor, the microprocessor therefore need not devote significant internal resources to prioritizing the interrupt request signals.

Abstract: The dual microprocessor system includes one microprocessor configured to perform wireless telephony functions and another configured to perform personal digital assistant (PDA) functions and other non-telephony functions. A memory system and a digital signal processor (DSP) are shared by the microprocessors. By providing a shared memory system, data required by both data microprocessors is conveniently available to both of the microprocessors and their peripheral components thereby eliminating the need to provide separate memory subsystems and further eliminating the need to transfer data back and forth between the separate memory subsystems. By providing a shared DSP, separate DSP devices need not be provided, yet both microprocessors can take advantage of the processing power of the DSP. In a specific example described herein, the microprocessors selectively program the DSP to perform, for example, vocoder functions, voice recognition functions, handwriting recognition functions, and the like.

Abstract: A microprocessor system having an interrupt controller is provided for use in a mobile communications device. Peripheral processing units generate interrupt requests for sending to the microprocessor. The microprocessor has components for responding to interrupt requests by interrupting current processing and performing an interrupt service routine associated with the interrupt request. The interrupt controller receives interrupt requests directed to the microprocessor from the peripheral processing units and for prioritizes the interrupt requests on behalf of the microprocessor. By providing an interrupt controller for prioritizing interrupt requests on behalf of the microprocessor, the microprocessor therefore need not devote significant internal resources to prioritizing the interrupt request signals.

Abstract: The flash and SRAM memory are embedded within an application specific integrated circuit (ASIC) to provide improved access times and also reduce overall power consumption of a mobile telephone employing the ASIC. The flash memory system includes a flash memory array configured to provide a set of individual flash macros and a flash memory controller for accessing the flash macros. The flash memory controller includes a read while writing unit for writing to one of the flash macros while simultaneously reading from another of the flash macros. By permitting read while writing, read operations need not be deferred until completion of pending write operations. The flash memory controller also includes programmable wait state registers. Each wait state register stores a programmable number of flash bus wait states associated with a portion of the flash memory.

Abstract: The flash and SRAM memory are embedded within an application specific integrated circuit (ASIC) to provide improved access times and also reduce overall power consumption of a mobile telephone employing the ASIC. The flash memory system includes a flash memory array configured to provide a set of individual flash macros and a flash memory controller for accessing the flash macros. The flash memory controller includes a read while writing unit for writing to one of the flash macros while simultaneously reading from another of the flash macros. By permitting read while writing, read operations need not be deferred until completion of pending write operations. The flash memory controller also includes programmable wait state registers. Each wait state register stores a programmable number of flash bus wait states associated with a portion of the flash memory.

Abstract: The flash and SRAM memory are embedded within an application specific integrated circuit (ASIC) to provide improved access times and also reduce overall power consumption of a mobile telephone employing the ASIC. The flash memory system includes a flash memory array configured to provide a set of individual flash macros and a flash memory controller for accessing the flash macros. The flash memory controller includes a read while writing unit for writing to one of the flash macros while simultaneously reading from another of the flash macros. By permitting read while writing, read operations need not be deferred until completion of pending write operations. The flash memory controller also includes programmable wait state registers. Each wait state register stores a programmable number of flash bus wait states associated with a portion of the flash memory.