Abstract: An integrated circuit such as a video controller may be provided with core logic circuitry using CMOS technology which may be operated at different supply voltages such as 3.3 or 5 Volts. At lower supply voltages, the CMOS circuitry may run slower. For a video controller, certain higher resolution, pixel depths, and refresh rates may require high speed operation of the video controller. A monitoring circuit monitors the video mode, pixel resolution, pixel depth, and refresh rate and determines which supply voltage may be used to operate the video controller at such levels. An output signal from the monitoring circuit may be used by a switching circuit to supply an appropriate supply voltage to the integrated circuit. At lower performance levels, the integrated circuit may be operated at lower voltages to conserve power.

Abstract: The display controller of the present invention reduces power consumption by suppressing clock signals to a display memory (comprising SGRAM or SDRAM) between screen refreshes and memory accesses. The present invention takes advantage of power-down modes provided for SGRAM and/or SDRAM memories which are used in the prior art to place a memory in an active suspend mode. Further energy savings are realized and memory bandwidth increased when using a display memory comprising two banks. When one bank of memory is being accessed, the other bank of memory is precharged and activated. Succeeding pages of memory are placed in alternate banks of display memory. Thus, then data is to be accessed from a next page of memory, the corresponding bank is already charged and ready to be accessed.