Patents by Inventor Sagheer Ahmad
Sagheer Ahmad has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20100030500Abstract: Provided are systems, methods, and computer program products for regulating power consumption in application-specific integrated circuits (ASICs)—such as, for example, a graphics processing unit. In such a method, a value of a leakage current of an ASIC is received from computer-readable information contained in the ASIC. One or more operational parameters of the ASIC—such as, for example, a supply voltage to the ASIC, a engine speed of the ASIC, and/or a fan speed of a fan used to cool the ASIC—are adjusted based on the value of the leakage current of the ASIC. Optionally, the one or more operational parameters may also be adjusted based on a type of application running on the ASIC. In addition, a supply voltage to the ASIC may (optionally) be shut off if the temperature of the ASIC exceeds a threshold.Type: ApplicationFiled: November 11, 2008Publication date: February 4, 2010Inventors: Gamal REFAI-AHMED, Sagheer AHMAD
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Publication number: 20090312874Abstract: Methods and systems for processing memory lookup requests are provided. In an embodiment, an integrated circuit includes an input configured to receive a first control signal and an output module configured to generate an output signal based at least on the first control signal and a second control signal generated based at least on a measured temperature of the IC. The output signal is configured to control a cooling device.Type: ApplicationFiled: June 11, 2008Publication date: December 17, 2009Applicant: Advanced Micro Devices Inc.Inventors: Jeffrey HERMAN, Sagheer AHMAD
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Patent number: 7227376Abstract: An impedance compensation circuit generates per-group pull-up impedance information and per-group pull-down impedance information to calibrate a plurality of input/output pads and dynamically updates impedance information on a per channel basis. A group refers to a group of I/O pads having similar output drive strengths in a channel. A channel refers to all I/O pads, which collectively provide a bus interface to an external device. For example, all the I/O pads interfacing with a memory module may be grouped into a channel, and address I/O pads in a channel may be arranged into a “group.” Memory I/O pads may be grouped together into a channel since memory interface pads have input/output characteristics that may be different from those of other types of I/O pads in the chip. According to one embodiment, per-group programmable offset information provides calibration information that may be different for each group in each channel.Type: GrantFiled: November 5, 2004Date of Patent: June 5, 2007Assignee: ATI Technologies Inc.Inventors: Sagheer Ahmad, Lin Chen, Sam Huynh, Shu-Shia Chow, Joe Macri
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Patent number: 7222251Abstract: An idle mode system has a clock gating circuit, a bus interface unit, memory interfaces and an interrupt and idle control unit. The clock gating circuit receives a first clock and designated idle-acknowledge signals. The clock gating circuit produces a second clock signal based on the first clock signal when fewer than all designated idle-acknowledge signals are received. The clock gating circuit produces no second clock signal when all designated idle-acknowledge signals are received. The bus interface unit receives bus access requests and receives the first and second clock signals. When a bus access request is made, the bus interface unit de-asserts its idle-acknowledge signal and passes the bus access request. The memory interfaces operate on the second clock. One interface receives the bus access request from the bus interface unit, withdraws its idle-acknowledge signal, processes the bus access request, and re-asserts its idle-acknowledge signal upon completion.Type: GrantFiled: February 5, 2003Date of Patent: May 22, 2007Assignee: Infineon Technologies AGInventors: Sagheer Ahmad, Erik Norden, Rob Ober
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Patent number: 7159103Abstract: A loop instruction, at least one target instruction, and an associated trigger address are cached during loop entry. During each loop iteration, the processor predicts whether the loop will be taken or not-taken in a subsequent iteration. When pre-fetch of the cached loop instruction is subsequently detected (i.e., by comparing the trigger address with the current program counter value), the loop taken/not-taken prediction is used to fetch either loop body instructions (when predicted taken) or fall-through instructions (when predicted not-taken). The cached loop instruction is then executed and the loop taken/not-taken prediction is verified using a dedicated loop execution circuit while a penultimate loop body instruction is executed in the processor execution stage (pipeline). When a previous loop taken prediction is verified, the cached target instruction is executed, and then the fetched loop body instructions are executed.Type: GrantFiled: March 24, 2003Date of Patent: January 2, 2007Assignee: Infineon Technologies AGInventors: Sagheer Ahmad, Matthias Knoth, Roger D. Arnold
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Patent number: 7149926Abstract: An embedded processor having a programmable trace port that selectively limits the amount of trace information passed from the processor core to an output buffer, and selectively controls the rate at which the trace information is output from the output buffer to an off-chip debug system. A configurable on-chip filter circuit selectively passes data and program information based on a wide range of user-defined combinations and/or sequences of trigger events (e.g., instruction addresses/types or data addresses/values). The filtered trace information is then compressed using separate data and program compression circuits, and passed to separate data and program output buffer. The data output buffer includes an adjustable read (output) rate (e.g., one-half or one-quarter of the processor core clock cycle), and allows a user to select between one or two output pointers.Type: GrantFiled: May 22, 2003Date of Patent: December 12, 2006Assignee: Infineon Technologies AGInventors: Sagheer Ahmad, Robert E. Ober
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Publication number: 20060106948Abstract: The disclosure relates to a programmable virtual memory client, that includes programmable control logic configured to generate at least one data pattern sequence from a number of stored data patterns. Additionally, the virtual memory client includes virtual memory client control logic configured to use the generated at least one data pattern sequence to at least one of read from and write to at least one memory device. A method includes generating at least one data pattern sequence from a number of stored data patterns and writing and reading the data pattern sequence from and to a memory device.Type: ApplicationFiled: November 12, 2004Publication date: May 18, 2006Applicant: ATI Technologies, Inc.Inventors: Sagheer Ahmad, Eric Scott, Joe Macri, Dan Shimizu
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Publication number: 20060097749Abstract: An impedance compensation circuit generates per-group pull-up impedance information and per-group pull-down impedance information to calibrate a plurality of input/output pads and dynamically updates impedance information on a per channel basis. A group refers to a group of I/O pads having similar output drive strengths in a channel. A channel refers to all I/O pads, which collectively provide a bus interface to an external device. For example, all the I/O pads interfacing with a memory module may be grouped into a channel, and address I/O pads in a channel may be arranged into a “group.” Memory I/O pads may be grouped together into a channel since memory interface pads have input/output characteristics that may be different from those of other types of I/O pads in the chip. According to one embodiment, per-group programmable offset information provides calibration information that may be different for each group in each channel.Type: ApplicationFiled: November 5, 2004Publication date: May 11, 2006Applicant: ATI Technologies, Inc.Inventors: Sagheer Ahmad, Lin Chen, Sam Huynh, Shu-Shia Chow, Joe Macri
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Patent number: 7010672Abstract: A digital processor having a programmable breakpoint/watchpoint (BWP) trigger circuit that generates BWP triggers in response to user-defined combinations and/or sequences of trigger events. Several trigger event detection registers generate pre-trigger signals when stored trigger values (e.g., instruction addresses or data addresses/values) match addresses/values transmitted on busses within the processor core. Sum-of-products circuits generate intermediate combinational trigger signals in accordance with user-defined combinations of the pre-trigger signals. A finite state machine generates an intermediate sequential trigger signal in response to user-defined sequences of the intermediate combinational trigger signals. Either the intermediate combinational trigger signals or the intermediate sequential trigger signal are selectively passed to an action generator, which transmits an associated breakpoint or watchpoint trigger signal to a decode stage of the processor core or other destination.Type: GrantFiled: December 11, 2002Date of Patent: March 7, 2006Assignee: Infineon Technologies AGInventors: Sagheer Ahmad, Anand Shirwal
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Publication number: 20040250164Abstract: An embedded processor having a programmable trace port that selectively limits the amount of trace information passed from the processor core to an output buffer, and selectively controls the rate at which the trace information is output from the output buffer to an off-chip debug system. A configurable on-chip filter circuit selectively passes data and program information based on a wide range of user-defined combinations and/or sequences of trigger events (e.g., instruction addresses/types or data addresses/values). The filtered trace information is then compressed using separate data and program compression circuits, and passed to separate data and program output buffer. The data output buffer includes an adjustable read (output) rate (e.g., one-half or one-quarter of the processor core clock cycle), and allows a user to select between one or two output pointers.Type: ApplicationFiled: May 22, 2003Publication date: December 9, 2004Applicant: Infineon Technologies North America Corp.Inventors: Sagheer Ahmad, Robert E. Ober
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Publication number: 20040193858Abstract: A loop instruction, at least one target instruction, and an associated trigger address are cached during loop entry. During each loop iteration, the processor predicts whether the loop will be taken or not-taken in a subsequent iteration. When pre-fetch of the cached loop instruction is subsequently detected (i.e., by comparing the trigger address with the current program counter value), the loop taken/not-taken prediction is used to fetch either loop body instructions (when predicted taken) or fall-through instructions (when predicted not-taken). The cached loop instruction is then executed and the loop taken/not-taken prediction is verified using a dedicated loop execution circuit while a penultimate loop body instruction is executed in the processor execution stage (pipeline). When a previous loop taken prediction is verified, the cached target instruction is executed, and then the fetched loop body instructions are executed.Type: ApplicationFiled: March 24, 2003Publication date: September 30, 2004Applicant: Infineon Technologies North America Corp.Inventors: Sagheer Ahmad, Matthias Knoth, Roger D. Arnold
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Publication number: 20040153678Abstract: An idle mode system has a clock gating circuit, a bus interface unit, memory interfaces and an interrupt and idle control unit. The clock gating circuit receives a first clock and designated idle-acknowledge signals. The clock gating circuit produces a second clock signal based on the first clock signal when fewer than all designated idle-acknowledge signals are received. The clock gating circuit produces no second clock signal when all designated idle-acknowledge signals are received. The bus interface unit receives bus access requests and receives the first and second clock signals. When a bus access request is made, the bus interface unit de-asserts its idle-acknowledge signal and passes the bus access request. The memory interfaces operate on the second clock. One interface receives the bus access request from the bus interface unit, withdraws its idle-acknowledge signal, processes the bus access request, and re-asserts its idle-acknowledge signal upon completion.Type: ApplicationFiled: February 5, 2003Publication date: August 5, 2004Applicant: Infineon Technologies North America Corp.Inventors: Sagheer Ahmad, Erik Norden, Rob Ober
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Publication number: 20040117605Abstract: A digital processor having a programmable breakpoint/watchpoint (BWP) trigger circuit that generates BWP triggers in response to user-defined combinations and/or sequences of trigger events. Several trigger event detection registers generate pre-trigger signals when stored trigger values (e.g., instruction addresses or data addresses/values) match addresses/values transmitted on busses within the processor core. Sum-of-products circuits generate intermediate combinational trigger signals in accordance with user-defined combinations of the pre-trigger signals. A finite state machine generates an intermediate sequential trigger signal in response to user-defined sequences of the intermediate combinational trigger signals. Either the intermediate combinational trigger signals or the intermediate sequential trigger signal are selectively passed to an action generator, which transmits an associated breakpoint or watchpoint trigger signal to a decode stage of the processor core or other destination.Type: ApplicationFiled: December 11, 2002Publication date: June 17, 2004Applicant: Infineon Technologies North America Corp.Inventors: Sagheer Ahmad, Anand Shirwal