Abstract: The present disclosure generally relates to a resistor structure having a charge control layer. In an example, an integrated circuit includes a semiconductor substrate, a dielectric layer, a first contact, a second contact, and a charge control layer. The semiconductor substrate includes a semiconductor hetero-structure. The dielectric layer is disposed over the semiconductor substrate. The first contact is disposed through the dielectric layer and contacting the semiconductor hetero-structure. The second contact is disposed through the dielectric layer and contacting the semiconductor hetero-structure. The second contact is disposed laterally separated from the first contact. The charge control layer is disposed over the semiconductor hetero-structure and laterally between the first contact and the second contact. At least a portion of the dielectric layer is disposed between the charge control layer and the semiconductor hetero-structure.

Abstract: An integrated circuit (IC) including a semiconductor surface layer of a substrate including functional circuitry having circuit elements formed in the semiconductor surface layer configured together with a Metal-Insulator-Metal capacitor (MIM) capacitor on the semiconductor surface layer for realizing at least one circuit function. The MIM capacitor includes a multilevel bottom capacitor plate having an upper top surface, a lower top surface, and sidewall surfaces that connect the upper and lower top surfaces (e.g., a bottom plate layer on a three-dimensional (3D) layer or the bottom capacitor plate being a 3D bottom capacitor plate). At least one capacitor dielectric layer is on the bottom capacitor plate. A top capacitor plate is on the capacitor dielectric layer, and there are contacts through a pre-metal dielectric layer to contact the top capacitor plate and the bottom capacitor plate.

Abstract: An integrated circuit (IC) including a semiconductor surface layer of a substrate including functional circuitry having circuit elements formed in the semiconductor surface layer configured together with a Metal-Insulator-Metal capacitor (MIM) capacitor on the semiconductor surface layer for realizing at least one circuit function. The MIM capacitor includes a multilevel bottom capacitor plate having an upper top surface, a lower top surface, and sidewall surfaces that connect the upper and lower top surfaces (e.g., a bottom plate layer on a three-dimensional (3D) layer or the bottom capacitor plate being a 3D bottom capacitor plate). At least one capacitor dielectric layer is on the bottom capacitor plate. A top capacitor plate is on the capacitor dielectric layer, and there are contacts through a pre-metal dielectric layer to contact the top capacitor plate and the bottom capacitor plate.