Abstract: Reference scaling, op amp balancing and chopper stabilization techniques for delta-sigma modulators of analog-to-digital converters are provided. For reference scaling, unit elements in a feedback digital-to-analog (DAC) converter are driven by a reference voltage or disconnected from active circuitry to realize three DAC levels. While disconnected, the unit elements deliver no charge to the device which results in power saving and a reduction in thermal noise. Op amp balancing involves down-sampling the quantizer output followed by up-sampling on the feedback path and filtering to hold a DAC value of the signal for a duration of a sampling period to generate the feedback signal. Chopper stabilization is performed by chopping an operational transconductance amplifier of the integrator at a chopping frequency equal to the sampling frequency.

Abstract: Reference scaling, op amp balancing and chopper stabilization techniques for delta-sigma modulators of analog-to-digital converters are provided. For reference scaling, unit elements in a feedback digital-to-analog (DAC) converter are driven by a reference voltage or disconnected from active circuitry to realize three DAC levels. While disconnected, the unit elements deliver no charge to the device which results in power saving and a reduction in thermal noise. Op amp balancing involves down-sampling the quantizer output followed by up-sampling on the feedback path and filtering to hold a DAC value of the signal for a duration of a sampling period to generate the feedback signal. Chopper stabilization is performed by chopping an operational transconductance amplifier of the integrator at a chopping frequency equal to the sampling frequency.

Abstract: A stacked switched resistance device has been developed. The stacked switched resistance device includes a plurality of segments connected in series. Each segment includes a resistor including an inherent parasitic capacitance, and a switch connected in series with the resistor, the switch being configured to connect and disconnect the resistor from the plurality of segments in response to a predetermined clock signal. An effective resistance of the stacked switched resistance device exceeds another effective resistance of at least one resistor with an equivalent inherent resistance that is connected in series to a single switch configured to connect and disconnect the at least one resistor in response to the predetermined clock signal.

Abstract: A current sensing system and delta sigma modulator architecture are discloses for sensing and digitizing a current input signal from a high impedance signal source with improve power efficiency. The delta sigma modulator integrates a signal condition stage within the delta sigma modulator feedback loop by utilizing a capacitive summation stage. For given gain, resolution, and bandwidth requirements, the delta sigma modulator architecture achieves reduced power consumption by advantageously reducing the number of nodes in the system that require a high dynamic range. Additionally, the delta sigma modulator has very high input impedance such that the input of the delta-sigma modulator can be connected directly to a high impedance signal source, without the need for a front-end pre-amplifier stage, or the like.

Abstract: A stacked switched resistance device has been developed. The stacked switched resistance device includes a plurality of segments connected in series. Each segment includes a resistor including an inherent parasitic capacitance, and a switch connected in series with the resistor, the switch being configured to connect and disconnect the resistor from the plurality of segments in response to a predetermined clock signal. An effective resistance of the stacked switched resistance device exceeds another effective resistance of at least one resistor with an equivalent inherent resistance that is connected in series to a single switch configured to connect and disconnect the at least one resistor in response to the predetermined clock signal.

Abstract: A microphone biasing circuit comprises a microphone connected between a first node and a first DC bias voltage, the microphone configured to provide a sensed voltage at the first node in response to sound; a first diode and a second diode, the first diode and the second diode connected antiparallel with one another between the first node and a second node, the second node having a second DC bias voltage; an amplifier having an input connected to the first node and an output connected to a third node, the amplifier configured to provide an output voltage to the third node based on the sensed voltage at the first node; and a feedback path connected from the third node to the second node. The feedback path comprises at least one element configured to couple alternating components of the output voltage at the third node to the second node.

Abstract: A microphone biasing circuit comprises a first amplifier having an output connected to a first node and an input connected to a second node; and a first feedback path connected from the first node to the second node. The first feedback path comprises a microphone having a first terminal connected to the first node and a second terminal connected to a third node, the microphone being configured to provide a sensed voltage at the first node in response to sound, the third node having a first DC bias voltage; and a first capacitor connected between the third node and the second node.

Abstract: A microphone biasing circuit comprises a microphone connected between a first node and a first DC bias voltage, the microphone configured to provide a sensed voltage at the first node in response to sound; a first diode and a second diode, the first diode and the second diode connected antiparallel with one another between the first node and a second node, the second node having a second DC bias voltage; an amplifier having an input connected to the first node and an output connected to a third node, the amplifier configured to provide an output voltage to the third node based on the sensed voltage at the first node; and a feedback path connected from the third node to the second node. The feedback path comprises at least one element configured to couple alternating components of the output voltage at the third node to the second node.

Abstract: A microphone biasing circuit comprises a first amplifier having an output connected to a first node and an input connected to a second node; and a first feedback path connected from the first node to the second node. The first feedback path comprises a microphone having a first terminal connected to the first node and a second terminal connected to a third node, the microphone being configured to provide a sensed voltage at the first node in response to sound, the third node having a first DC bias voltage; and a first capacitor connected between the third node and the second node.

Abstract: A capacitance measurement circuit cancels background capacitance while reducing charge leakage and supply ripples during reset phases and integrate phases. The capacitance measurement circuit operates a first switch into a linear mode causing a first resistance in the first switch, and after a delay, operates a second switch into a saturation mode causing a second resistance in parallel to the first resistance.

Abstract: A capacitance measurement circuit cancels background capacitance while reducing charge leakage and supply ripples during reset phases and integrate phases. The capacitance measurement circuit operates a first switch into a linear mode causing a first resistance in the first switch, and after a delay, operates a second switch into a saturation mode causing a second resistance in parallel to the first resistance.

Abstract: In a linear voltage regulator, a first stage outputs an output signal. The first stage is configured with a first switchable bias current, and is configured to receive a feedback signal. A second stage provides a regulated voltage output. A decoupling capacitor is coupled to the regulated voltage output. A feedback circuit is coupled with the second stage and configured to generate the feedback signal. A frequency compensation circuit includes a second switchable bias current. The frequency compensation circuit: pushes away an existing pole to a higher frequency when the first and second switchable bias currents are operated in a sleep mode; and creates a left-hand-side zero when the first and second switchable bias currents are operated in an active mode. The active mode comprises the first and second switchable bias currents supplying greater currents than are provided in the sleep mode.

Abstract: In a linear voltage regulator, a first stage outputs an output signal. The first stage is configured with a first switchable bias current, and is configured to receive a feedback signal. A second stage provides a regulated voltage output. A decoupling capacitor is coupled to the regulated voltage output. A feedback circuit is coupled with the second stage and configured to generate the feedback signal. A frequency compensation circuit includes a second switchable bias current. The frequency compensation circuit: pushes away an existing pole to a higher frequency when the first and second switchable bias currents are operated in a sleep mode; and creates a left-hand-side zero when the first and second switchable bias currents are operated in an active mode. The active mode comprises the first and second switchable bias currents supplying greater currents than are provided in the sleep mode.