Abstract: Reduced complexity encoders and related systems, apparatuses, and methods are disclosed. An apparatus includes a data storage device and a processing circuitry. The data storage device is to store a first data part of a transmit data frame. The transmit data frame is received from one or more higher network layers that are higher than a physical layer. The transmit data frame includes the first data part and a second data part. The second data part includes data bits having known values. The processing circuitry is to retrieve the first data part of the transmit data frame from the data storage device and determine parity vectors for the transmit data frame independently of the second data part responsive to the first data part.

Abstract: An apparatus comprises a data width converter and a forward error correction (FEC) decoder. The data width converter includes an input to receive an input data stream having an input bit width, a first output to produce a first output data stream having a first output bit width, and a second output to produce a second output data stream having at least a second output bit width. The FEC decoder includes an input to receive the second output data stream having the at least second output bit width. The FEC decoder includes an error correction output to produce one or more error correction values at least partially based on one or more FEC code words in the second output data stream. The one or more error correction values are for correction of one or more symbols, one or more partial symbols, or both, in the first output data stream having the first output bit width.

Abstract: An apparatus comprises a data width converter and a forward error correction (FEC) encoder. The data width converter includes an input to receive an input data stream at an input bit width, a first output to produce a first output data stream at a first output bit width, and a second output to produce a second output data stream at a second output bit width. The FEC encoder includes an input to receive the second output data stream at the second output bit width. The FEC encoder includes an output to produce parity bits at least partially based on multiple received symbols of the second output data stream having the second output bit width. The parity bits for insertion in the first output data stream having the first output bit width. In one or more examples, the data width converter is in a transmit data path, and the FEC encoder is in parallel with the transmit data path.

Abstract: Reduced complexity decoders with improved error correction and related systems, methods, and apparatuses are disclosed. An apparatus includes an input terminal and a processing circuitry. The input terminal is provided at a physical layer device to receive, from a network, a low density parity check (LDPC) frame including bits. The bits correspond to log-likelihood ratio (LLR) messages indicating probabilities that the bits have predetermined logic values. The processing circuitry is to saturate LLR values of a portion of the LLR messages corresponding to known bits of the LDPC frame to a highest magnitude value represented by the LLR messages, and pass the LLR messages between check nodes and message nodes. The message nodes correspond to the bits. The check nodes correspond to parity check equations of a parity check matrix.

Abstract: Reduced complexity encoders and related systems, apparatuses, and methods are disclosed. An apparatus includes a data storage device and a processing circuitry. The data storage device is to store a first data part of a transmit data frame. The transmit data frame is received from one or more higher network layers that are higher than a physical layer. The transmit data frame includes the first data part and a second data part. The second data part includes data bits having known values. The processing circuitry is to retrieve the first data part of the transmit data frame from the data storage device and determine parity vectors for the transmit data frame independently of the second data part responsive to the first data part.

Abstract: Reduced complexity decoders with improved error correction and related systems, methods, and apparatuses are disclosed. An apparatus includes an input terminal and a processing circuitry. The input terminal is provided at a physical layer device to receive, from a network, a low density parity check (LDPC) frame including bits. The bits correspond to log-likelihood ratio (LLR) messages indicating probabilities that the bits have predetermined logic values. The processing circuitry is to saturate LLR values of a portion of the LLR messages corresponding to known bits of the LDPC frame to a highest magnitude value represented by the LLR messages, and pass the LLR messages between check nodes and message nodes. The message nodes correspond to the bits. The check nodes correspond to parity check equations of a parity check matrix.