Abstract: Reduced manufacturing costs and wafer size, lower power consumption, and increased operating speed are achieved in memory circuits by providing a novel sense amplifier design that is most sensitive to voltages variations around the source voltage (V.sub.dd). The sense amplifier includes two inverters that are regeneratively cross-coupled through a circuit that is controlled by a system clock. The inverters are powered from the bit lines that couple the sense amplifier to a memory cell. Novel applications of the sense amplifier in memory circuits also are described.

Abstract: Maximum operating speed is achieved in an array of memory cells by performing both read and write operations within a single memory cycle. As outgoing data are read from the memory cells, incoming data are stored immediately in those cells. Once data are read from the memory cells, a latch signal is generated to trigger latching of the read data for output to a data bus. The same latch signal that is used to latch the read data initiates the writing of new data to the memory cells. Use of a single latch signal in this manner ensures that new data are not written to the memory cells until the existing data has been read from those cells.

Abstract: A tapped digital shift register suitable for use with a finite-impulse-response (FIR) filter in applications such as high-definition television is implemented using a random-access memory (RAM). The RAM contains x words having yz bits each, where x represents the number of elements in each section of the shift register, y represents the number of taps and z represents the number of bits in each element. Words are continuously read from and written back into the RAM. Before being written back, each word is modified by removing a z-bit portion from one end and appending a z-bit portion representing new information to the other end. The shift-register architecture disclosed is particularly suited for implementation on very-large-scale integrated circuits together with the FIR filter circuits.

Abstract: In a multiplier for binary numbers represented in two's complement notation, the need to perform sign-bit extension in order to combine the partial products is avoided by representing the value represented by the sign bits of all the partial products as a two's complement number in its own right. The bits of that number, rather than the original sign bits, are then used in the partial product addition. Since (as with all two's complement numbers) all the bits of the sign-bit-value word are guaranteed to have positive significance (except for the left-most one), the digits of the partial products can then be direcly added without the need for sign bit extension.

Abstract: In a telephone local loop transmission arrangement, data is communicated from the customer premises to the central office utilizing a multi-dimensional, passband signal illustratively at 480 kb/s and 1.544 Mb/s.