Abstract: A prefetch controller implements an upgrade when a real read access request hits the same memory bank and memory address as a previous prefetch request. In response per-memory bank logic promotes the priority of the prefetch request to that of a read request. If the prefetch request is still waiting to win arbitration, this upgrade in priority increases the likelihood of gaining access generally reducing the latency. If the prefetch request had already gained access through arbitration, the upgrade has no effect. This thus generally reduces the latency in completion of a high priority real request when a low priority speculative prefetch was made to the same address.

Abstract: A real request from a CPU to the same memory bank as a prior prefetch request is transmitted to the per-memory bank logic along with a kill signal to terminate the prefetch request. This avoids waiting for a prefetch request to complete before sending the real request to the same memory bank. The kill signal gates off any acknowledgement of completion of the prefetch request. This invention reduces the latency for completion of a high priority real request when a low priority speculative request to a different address in the same memory bank has already been dispatched.

Abstract: A hardware based wake-up scheme initiates memory power-up upon a normal access to a powered down memory. The access that triggered the power-up is buffered. Further accesses are stalled until the memory is completely powered up. The buffered access then proceeds to the memory and the processor is brought out of stall. In cases where the software does not directly control access to the memory, such as on a cache miss, this scheme avoids undesirable conditions due to access to powered down memories.

Abstract: A prefetch scheme in a shared memory multiprocessor disables the prefetch when an address falls within a powered down memory bank. A register stores a bit corresponding to each independently powered memory bank to determine whether that memory bank is prefetchable. When a memory bank is powered down, all bits corresponding to the pages in this row are masked so that they appear as non-prefetchable pages to the prefetch access generation engine preventing an access to any page in this memory bank. A powered down status bit corresponding to the memory bank is used for masking the output of the prefetch enable register. The prefetch enable register is unmodified. This also seamlessly restores the prefetch property of the memory banks when the corresponding memory row is powered up.

Abstract: This invention manages power down and wakeup of shared memories in a multiprocessor system. A register for each shared memory has bits corresponding to each master. When a master wants to power down a memory, it sets its corresponding bit in the register. A hardware power down controller for the memory bank powers the memory bank if any processor signals powering the memory bank. The hardware power down controller for the memory bank powers down the memory bank only if all processor signal powering down the memory bank. The hardware power down controller waits for all masters to set their corresponding bits in the register before initiating power down of the memories. Software running on any processor has a view of the shared memory independent of the other processors and no inter-processor communication is needed.

Abstract: This invention is a power management scheme for a shared memory multiprocessor system which splits the control logic between the master-specific logic and memory bank logic. Power-down is initiated from a central power-down controller. This central power-down controller informs the master and target specific logic. Further memory accesses are blocked. All pending activities complete. The central controller then proceeds to power down the memory and informs the master and target specific logic upon completion. No requests for wakeup are initiated by master-specific logic from the time a power-down request is received until the completion of power-down.

Abstract: A video decoder includes a memory (140) operable to hold entropy coded video data accessible as a bit stream, a processor (100) operable to issue at least one command for loose-coupled support and to issue at least one instruction for tightly-coupled support, a bit stream unit (110.1) coupled to said memory (140) and to said processor (100) and responsive to at least one command to provide the loose-coupled support and command-related accelerated processing of the bit stream, and a second bit stream unit (110.2) coupled to said memory (140) and to said processor (100) and responsive to said at least one instruction to provide the tightly-coupled support and instruction-related accelerated processing of the bit stream. Other encoding and decoding processors, circuits, devices, systems and processes are also disclosed.

Abstract: This invention transforms a circuit design at an asynchronous clock boundary using a flow involving register grouping, logic modification and level shifter and isolation cell insertion. The level shifter and isolation cell inserted are tested for proper location. The transformed circuit design is suitable for power consumption control by independent control of separate voltage domains.

Abstract: A hardware based wake-up scheme initiates memory power-up upon a normal access to a powered down memory. The access that triggered the power-up is buffered. Further accesses are stalled until the memory is completely powered up. The buffered access then proceeds to the memory and the processor is brought out of stall. In cases where the software does not directly control access to the memory, such as on a cache miss, this scheme avoids undesirable conditions due to access to powered down memories.

Abstract: This invention manages power down and wakeup of shared memories in a multiprocessor system. A register for each shared memory has bits corresponding to each master. When a master wants to power down a memory, it sets its corresponding bit in the register. A hardware power down controller for the memory bank powers the memory bank if any processor signals powering the memory bank. The hardware power down controller for the memory bank powers down the memory bank only if all processor signal powering down the memory bank. waits for all masters to set their corresponding bits in the register before initiating power down of the memories. Software running on any processor has a view of the shared memory independent of the other processors and no inter-processor communication is needed.

Abstract: A real request from a CPU to the same memory bank as a prior prefetch request is transmitted to the per-memory bank logic along with a kill signal to terminate the prefetch request. This avoids waiting for a prefetch request to complete before sending the real request to the same memory bank. The kill signal gates off any acknowledgement of completion of the prefetch request. This invention reduces the latency for completion of a high priority real request when a low priority speculative request to a different address in the same memory bank has already been dispatched.

Abstract: A prefetch controller implements an upgrade when a real read access request hits the same memory bank and memory address as a previous prefetch request. In response per-memory bank logic promotes the priority of the prefetch request to that of a read request. If the prefetch request is still waiting to win arbitration, this upgrade in priority increases the likelihood of gaining access generally reducing the latency. If the prefetch request had already gained access through arbitration, the upgrade has no effect. This thus generally reduces the latency in completion of a high priority real request when a low priority speculative prefetch was made to the same address.

Abstract: This invention is a power management scheme for a shared memory multiprocessor system which splits the control logic between the master-specific logic and memory bank logic. Power-down is initiated from a central power-down controller. This central power-down controller informs the master and target specific logic. Further memory accesses are blocked. All pending activities complete. The central controller then proceeds to power down the memory and informs the master and target specific logic upon completion. No requests for wakeup are initiated by master-specific logic from the time a power-down request is received until the completion of power-down.

Abstract: A prefetch scheme in a shared memory multiprocessor disables the prefetch when an address falls within a powered down memory bank. A register stores a bit corresponding to each independently powered memory bank to determine whether that memory bank is prefetchable. When a memory bank is powered down, all bits corresponding to the pages in this row are masked so that they appear as non-prefetchable pages to the prefetch access generation engine preventing an access to any page in this memory bank. A powered down status bit corresponding to the memory bank is used for masking the output of the prefetch enable register. The prefetch enable register is unmodified. This also seamlessly restores the prefetch property of the memory banks when the corresponding memory row is powered up.

Abstract: This invention transforms a circuit design at an asynchronous clock boundary using a flow involving register grouping, logic modification and level shifter and isolation cell insertion. The level shifter and isolation cell inserted are tested for proper location. The transformed circuit design is suitable for power consumption control by independent control of separate voltage domains.