Patents by Inventor Sakae Ito

Sakae Ito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040051769
    Abstract: An image forming apparatus includes an image forming unit having an image forming portion positioned over a partition wall that vertically partitions a body frame above a cover plate. A second circuit board in which a tall electronic component-mounting side is upward directed is placed in a space between the partition wall and the cover plate. A first circuit board in which an electronic component-mounting side is downward directed is placed on a lateral side of the second circuit board. The first and second circuitp boards are placed in a stepwise manner so that the level of the first circuit board is higher than that of the second circuit board. A return path for reversely transporting a sheet is formed between the cover plate and the upper face of a return tray.
    Type: Application
    Filed: September 10, 2003
    Publication date: March 18, 2004
    Applicant: BROTHER KOGYO KABUSHIKI KAISHA
    Inventors: Shusaku Tsusaka, Sakae Ito
  • Patent number: 5724029
    Abstract: A communication control section is provided with a plurality of receiving channels (RXDA1 and RXDA2). An address separated by an address separating section constituting the RXDA1 is compared with a reference address denoting a token, and if the separated address corresponds thereto, an interruption is requested by an interruption processing section. An address separated by an address separating section constituting the RXDA2 is compared with a reference address denoting the station number of that particular station, and if the separated address corresponds thereto, the interruption is similarly requested. When the interruption has been requested, the processing of a CPU transfers from the processing of a main routine by a main routine processing section to an interruption processing by an interruption processing section.
    Type: Grant
    Filed: October 17, 1995
    Date of Patent: March 3, 1998
    Assignees: Toyota Jidosha Kabushiki Kaisha, Sharp Kabushiki Kaisha
    Inventors: Noriyuki Takao, Hidetoshi Takano, Sakae Ito, Naoki Okamura
  • Patent number: 4121007
    Abstract: A novel printed circuit board with a circuit of high precision having a polymer coat layer between a base and a dispersion imaging material layer and a pattern circuit on undispersed portions of the dispersion imaging material layer. Such a printed circuit board is prepared by a simplified process which comprises essentially two steps, namely, exposure of the dispersion imaging material through a circuit pattern mask to obtain a pattern circuit of the unexposed portions and conductive metal plating wherein said unexposed portions are selectively deposited with the conductive metal due to the specific effect of provision of the polymer coat layer directly under the dispersion imaging material layer.
    Type: Grant
    Filed: August 10, 1976
    Date of Patent: October 17, 1978
    Assignee: Asahi Kasei Kogyo Kabushiki Kaisha
    Inventors: Hidehiko Kobayashi, Tatsumi Arakawa, Tetsuo Shiga, Kaoru Ohmura, Sakae Ito