Abstract: There has been a problem in semiconductor apparatuses of related art in which a circuit operation cannot be returned after a reverse current occurred. In one embodiment, a semiconductor apparatus includes a timer block configured to count up a count value to a predetermined value in response to a control signal being enabled, the control signal instructing a power MOS transistor to be turned on, and a protection transistor including a drain connected to a gate of the power MOS transistor, a source and a back gate connected to a source of the power MOS transistor, and an epitaxial layer in which the power MOS transistor is formed, the epitaxial layer being supplied with a power supply voltage. The protection transistor short-circuits the source and gate of the power MOS transistor in response to an output voltage of the power MOS transistor meeting a predetermined condition and the count value reaching the predetermined value.

Abstract: There has been a problem in semiconductor apparatuses of related art in which a circuit operation cannot be returned after a reverse current occurred. In one embodiment, a semiconductor apparatus includes a timer block configured to count up a count value to a predetermined value in response to a control signal being enabled, the control signal instructing a power MOS transistor to be turned on, and a protection transistor including a drain connected to a gate of the power MOS transistor, a source and a back gate connected to a source of the power MOS transistor, and an epitaxial layer in which the power MOS transistor is formed, the epitaxial layer being supplied with a power supply voltage. The protection transistor short-circuits the source and gate of the power MOS transistor in response to an output voltage of the power MOS transistor meeting a predetermined condition and the count value reaching the predetermined value.

Abstract: A driver IC (Integrated Circuit) includes a power supply terminal; an output terminal to be coupled to a load element; a connection node on a current path between the power supply terminal and the output terminal; a substrate resistance, having one end coupled to the connection node; an output transistor including a gate, wherein the output transistor is coupled in series with the substrate resistance through the connection node; a resistance, having one end coupled to an other end of the substrate resistance; and a voltage detecting circuit configured to detect a voltage depending on a voltage between the one end of the substrate resistance and the other end of the substrate resistance, and to output an output signal, which is as an output of the voltage detecting circuit, to the gate of the output transistor.

Abstract: A power semiconductor device includes an output transistor, a control circuit connected with a gate of the output transistor, a first discharge route from a first node to a ground terminal, and a second discharge route from the first node to the ground terminal. In a usual turn-off, only the first discharge route is used. When a load abnormality occurs, both of the first and second discharge routes are used. The second discharge route contains a discharge transistor and a countercurrent prevention device. The discharge transistor is connected between the first node and the second node. The countercurrent prevention device prevents a flow of current from the third node to the second node. At least, in an OFF period, the control circuit sets the gate voltage of the discharge transistor to a high level.

Abstract: A driver IC (Integrated Circuit) includes a power supply terminal; an output terminal to be coupled to a load element; a connection node on a current path between the power supply terminal and the output terminal; a substrate resistance, having one end coupled to the connection node; an output transistor including a gate, wherein the output transistor is coupled in series with the substrate resistance through the connection node; a resistance, having one end coupled to an other end of the substrate resistance; and a voltage detecting circuit configured to detect a voltage depending on a voltage between the one end of the substrate resistance and the other end of the substrate resistance, and to output an output signal, which is as an output of the voltage detecting circuit, to the gate of the output transistor.

Abstract: A semiconductor high-side driver including; an input terminal; an output terminal to be coupled to a load element; an output MOS transistor having a drain coupled to a power supply terminal, a source coupled to the output terminal and a gate; a sense MOS transistor having a drain coupled to the power supply terminal, a gate coupled to the gate of the output MOS transistor and a source; a control circuit coupled to the input terminal and provides a control signal to the gate of the output MOS transistor; and a voltage detection circuit which includes: a threshold voltage generation circuit having a first terminal coupled to the power supply terminal and a second terminal which generates a voltage lower than a voltage of the power supply terminal by a threshold voltage; and a comparator.

Abstract: A semiconductor high-side driver including; an input terminal; an output terminal to be coupled to a load element; an output MOS transistor having a drain coupled to a power supply terminal, a source coupled to the output terminal and a gate; a sense MOS transistor having a drain coupled to the power supply terminal, a gate coupled to the gate of the output MOS transistor and a source; a control circuit coupled to the input terminal and provides a control signal to the gate of the output MOS transistor; and a voltage detection circuit which includes: a threshold voltage generation circuit having a first terminal coupled to the power supply terminal and a second terminal which generates a voltage lower than a voltage of the power supply terminal by a threshold voltage; and a comparator.

Abstract: A semiconductor device includes an N-type semiconductor region, a back electrode, first and second P-type base regions, first and second N+ diffusion layers, a gate insulating film, a gate electrode and a voltage detecting circuit. The first N+ diffusion layer functions as a source of an output MOS transistor and functions as a source of a sense MOS transistor. The gate electrode is provided to oppose the N-type semiconductor region and the first and second P-type base regions through the gate insulating film 40. A load current flows between the back electrode and the first N+ diffusion layer. The voltage detecting circuit generates a detection signal.

Abstract: A power semiconductor device includes an output transistor, a control circuit connected with a gate of the output transistor, a first discharge route from a first node to a ground terminal, and a second discharge route from the first node to the ground terminal. In a usual turn-off, only the first discharge route is used. When a load abnormality occurs, both of the first and second discharge routes are used. The second discharge route contains a discharge transistor and a countercurrent prevention device. The discharge transistor is connected between the first node and the second node. The countercurrent prevention device prevents a flow of current from the third node to the second node. At least, in an OFF period, the control circuit sets the gate voltage of the discharge transistor to a high level.

Abstract: A semiconductor device includes an N-type semiconductor region, a back electrode, first and second P-type base regions, first and second N+ diffusion layers, a gate insulating film, a gate electrode and a voltage detecting circuit. The first N+ diffusion layer functions as a source of an output MOS transistor and functions as a source of a sense MOS transistor. The gate electrode is provided to oppose the N-type semiconductor region and the first and second P-type base regions through the gate insulating film 40. A load current flows between the back electrode and the first N+ diffusion layer. The voltage detecting circuit generates a detection signal.

Abstract: A power semiconductor device includes an output transistor, a control circuit connected with a gate of the output transistor, a first discharge route from a first node to a ground terminal, and a second discharge route from the first node to the ground terminal. In a usual turn-off, only the first discharge route is used. When a load abnormality occurs, both of the first and second discharge routes are used. The second discharge route contains a discharge transistor and a countercurrent prevention device. The discharge transistor is connected between the first node and the second node. The countercurrent prevention device prevents a flow of current from the third node to the second node. At least, in an OFF period, the control circuit sets the gate voltage of the discharge transistor to a high level.

Abstract: A power semiconductor device includes an output transistor, a control circuit connected with a gate of the output transistor, a first discharge route from a first node to a ground terminal, and a second discharge route from the first node to the ground terminal. In a usual turn-off, only the first discharge route is used. When a load abnormality occurs, both of the first and second discharge routes are used. The second discharge route contains a discharge transistor and a countercurrent prevention device. The discharge transistor is connected between the first node and the second node. The countercurrent prevention device prevents a flow of current from the third node to the second node. At least, in an OFF period, the control circuit sets the gate voltage of the discharge transistor to a high level.

Abstract: A power semiconductor device has: an output transistor connected between a power-supply terminal and an output terminal; a gate charge-discharge circuit configured to charge/discharge a first node connected to a gate of the output transistor to ON/OFF control the output transistor; a short switch circuit connected between the first node and the output terminal; and a short control circuit configured to control the short switch circuit. In the turn-ON period, the ON period and the turn-OFF period, the short control circuit cuts off electrical connection between the first node and the output terminal through the short switch circuit. In the OFF period, the short control circuit electrically connects the first node and the output terminal through the short switch circuit.

Abstract: An overcurrent detection circuit in accordance with an exemplary aspect of the present invention includes a detection transistor, a potential difference setting unit, and a first transistor whose current value is controlled by the potential difference setting unit. Further, the potential difference setting unit includes a first depletion type transistor, a power-supply voltage being supplied to the drain of the first depletion type transistor, and the gate and source of the first depletion type transistor being connected to the gate of the first transistor, a second transistor, the drain and gate of the second transistor being connected to the gate of the first transistor, and a second depletion type transistor provided on the current path between the sources of the first transistor and the second transistor, the gate and drain of the second depletion type transistor being connected to the source of the detection transistor.

Abstract: A power semiconductor device has: an output transistor connected between a power-supply terminal and an output terminal; a gate charge-discharge circuit configured to charge/discharge a first node connected to a gate of the output transistor to ON/OFF control the output transistor; a short switch circuit connected between the first node and the output terminal; and a short control circuit configured to control the short switch circuit. In the turn-ON period, the ON period and the turn-OFF period, the short control circuit cuts off electrical connection between the first node and the output terminal through the short switch circuit. In the OFF period, the short control circuit electrically connects the first node and the output terminal through the short switch circuit.

Abstract: An overcurrent detection circuit in accordance with an exemplary aspect of the present invention includes a detection transistor, a potential difference setting unit, and a first transistor whose current value is controlled by the potential difference setting unit. Further, the potential difference setting unit includes a first depletion type transistor, a power-supply voltage being supplied to the drain of the first depletion type transistor, and the gate and source of the first depletion type transistor being connected to the gate of the first transistor, a second transistor, the drain and gate of the second transistor being connected to the gate of the first transistor, and a second depletion type transistor provided on the current path between the sources of the first transistor and the second transistor, the gate and drain of the second depletion type transistor being connected to the source of the detection transistor.

Abstract: In relation to the conventional semiconductor device provided with a plurality of FETs, there is room for improving the pair accuracy of the FET-pair. A semiconductor device includes a first FET, a second FET, a third FET and a fourth FET. The four FETs are provided in an active region (certain region). The four have each of gate electrodes, respectively. Each of the gate electrodes are arranged along a circle in this sequence in plan view. The four FETs have the substantially same geometry.

Abstract: A highly precise temperature compensation is applied in the detection of overcurrent. A control circuit detects a potential difference produced across a wire owing to the resistance of the wire and a load current that flows into the wire, which connects an NMOS transistor and an output terminal, and controls the NMOS transistor so as to limit the load current if the potential difference exceeds a prescribed value. The control circuit 20 includes a first diode group having a first end from which a first current is passed in a forward direction by a first current source and a second end connected to a first end of the wire, and a second diode group having a first end from which a second current is passed in a forward direction by a second current source and a second end connected to a second end of the wire.

Abstract: A highly precise temperature compensation is applied in the detection of overcurrent. A control circuit detects a potential difference produced across a wire owing to the resistance of the wire and a load current that flows into the wire, which connects an NMOS transistor and an output terminal, and controls the NMOS transistor so as to limit the load current if the potential difference exceeds a prescribed value. The control circuit 20 includes a first diode group having a first end from which a first current is passed in a forward direction by a first current source and a second end connected to a first end of the wire, and a second diode group having a first end from which a second current is passed in a forward direction by a second current source and a second end connected to a second end of the wire.

Abstract: In relation to the conventional semiconductor device provided with a plurality of FETS, there is room for improving the pair accuracy of the FET-pair. A semiconductor device includes a first FET, a second FET, a third FET and a fourth FET. The four FETs are provided in an active region (certain region). The four have each of gate electrodes, respectively. Each of the gate electrodes are arranged along a circle in this sequence in plan view. The four FETs have the substantially same geometry.