Patents by Inventor Sakae Yokokawa

Sakae Yokokawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6344616
    Abstract: A cable for use in connection between integrated circuit elements each having terminals. The cable body has an insulator and a plurality of conductors buried in the insulator to have a matrix pattern in section. The cable body has longitudinal end faces as mounting surfaces which are for mounting the integrated circuit elements, respectively. On each of the mounting surfaces, a plurality of conductor pads are formed to connect with the conductors. The conductor pads are connected to the terminals of each of the integrated circuit elements, respectively.
    Type: Grant
    Filed: June 27, 2000
    Date of Patent: February 5, 2002
    Assignee: NEC Corporation
    Inventor: Sakae Yokokawa
  • Patent number: 5322593
    Abstract: A layered structure comprising wiring layers and polyimide layers is formed on a ceramics board and a layered structure comprising wiring layers and polyimide layers is formed on an aluminum board. Both the structures are bonded together through adhesives to bring metal bumps formed on the former structure into electric contact with metal bumps formed on the surface of the latter structure and thereafter the aluminum board is removed.
    Type: Grant
    Filed: November 20, 1992
    Date of Patent: June 21, 1994
    Assignee: NEC Corporation
    Inventors: Shinichi Hasegawa, Sakae Yokokawa
  • Patent number: 5110654
    Abstract: A ceramic multilayer wiring substrate having a stack of a plurality of ceramic sheets each being formed with through holes which are connected to one another by a conductive paste buried in said through holes. Among the ceramic sheets, those which constitute an intermediate layer portion each is formed with a plurality of parallel through holes which are spaced apart in the direction perpendicular to the direction of thickness of the ceramic sheet. With such through holes, the substrate reduces the resistance in the intermediate layer portion and, therefore, the conduction resistance of the entire through holes.
    Type: Grant
    Filed: July 16, 1990
    Date of Patent: May 5, 1992
    Assignee: NEC Corporation
    Inventor: Sakae Yokokawa