Abstract: In a data processing device, a fixed-point position control unit determines, as first control. The fixed-point position control unit causes a detection calculation unit to perform calculation processing on processing target data at a processing point in time. The saturation rate control unit instructs, as second control to be repeated by the fixed-point position control unit, the fixed-point position control unit to move at least the fixed-point position as control to increase a lower limit saturation rate proportional to a magnitude of a counted lower limit counter value with respect to a result of the first control. The fixed-point position control unit performs, as the second control, a predetermined determination on the basis of the instruction from the saturation rate control unit and the metadata, determines the fixed-point position moved for each layer, and causes calculation processing to be performed.

Abstract: A calculation unit (22) sets each frame, of a moving image including a plurality of frames, as a target frame, calculates a motion vector with reference to a reference frame over an entirety of the target frames, and calculates an index indicating a magnitude of change between a key frame and the target frame, which is represented by using the motion vector, a judgement unit (25) judges whether or not the calculated index is equal to or greater than a predetermined threshold value, a first detection unit (27) detects a region indicating an object from the target frame by using an object detection model in a case in which the index is equal to greater than the threshold value, a second detection unit (28) detects a region on the target frame, which is obtained by correcting a position of a region detected in the reference frame by using the motion vector in a case in which the index is less than the threshold value, and an output unit (30) outputs information of the region detected by the first detection unit

Abstract: An object detection device 10 includes an entire processing unit 110 that obtains first metadata for the entire input image by scaling the input image and performing object detection processing, a divided image narrowing unit 120 that narrows down the input image into a predetermined number of selected divided images from a group of divided images obtained by dividing the input image, a division processing unit 130 that obtains second metadata by performing object detection processing for each of the selected divided images, and a synthesis processing unit 140 that removes the second metadata obtained by the division processing unit 130 that overlaps the first metadata obtained by the entire processing unit 110, and synthesizes the first metadata not removed and the first meta data obtained by the entire processing unit 110 to output the meta data.

Abstract: An embodiment is a packet capture device including a first local timer synchronized with an external global timer, a second local timer, a time stamp assign unit for assigning a time stamp to a inputted packet signal based on the second local timer, a filter unit for selecting the packet signal to which the time stamp is assigned, a capture file generation unit for receiving the selected packet signal, and a storage unit for storing a capture file generated in the capture file generation unit, wherein the capture file generation unit calculate a difference between a timer value of the first local timer and a timer value of the second local timer to correct the time stamp value on the basis of the difference.

Abstract: A packet capture system for capturing packets flowing in a capture target network, and a plurality of stages of packet distribution devices for capturing packet of a specific flow are cascade-connected, packet distribution devices identify a capture target flow by analyzing inputted packets, packet distribution devices other than a last-stage packet distribution device are configured to distribute packets to capture packets of a flow to be captured and output packets of a flow not to be captured to a next-stage packet distribution device, and the last-stage packet distribution device is configured to filter the packets of the flow to be captured and to discard the packets of the flow not to be captured.

Abstract: The integration unit 26, using configuration information of the convolutional neural network model and each filter used in each convolutional layer of the convolutional neural network model as inputs, deletes one or more pieces of activation function processing performed between the plurality of convolutional layers and integrates a plurality of filters used in the plurality of convolutional layers.

Abstract: An embodiment is a data processor including a decimal point position control circuit configured to set a decimal point position of N-bit (N is a natural number of 2 or more) fixed-length data corresponding to each of a plurality of layers constituting a multilayered neural network, and an arithmetic processing circuit configured to perform arithmetic processing corresponding to each of the plurality of layers constituting the multilayered neural network according to a processing algorithm of the multilayered neural network on the N-bit fixed-length data for which the decimal point position has been set by the decimal point position control circuit.

Abstract: A network load balancing apparatus has a data buffer for each communication path of a received packet's transfer destinations, calculates a first hash value using a field value contained in the packet, determines, based on the field value of the packet or the first hash value, a communication path of a transfer destination of the packet subject to external transfer control for transmission to a predetermined external server, determines, based on the first hash value, a communication path of a transfer destination of the packet to be subject to priority control, determines, based on a second hash value based on the first hash value, a communication path of a transfer destination of the packet to be subject to load balancing control, to match a preset load balancing situation of the data buffer, and transmits the packet to a data buffer corresponding to the communication path of the transfer destination.

Abstract: A network load balancing apparatus has a data buffer provided to each communication path of transfer destinations of a received packet and being associated with a virtual function, determines a destination virtual function based on a field value of the received packet, determines a communication path of a transfer destination of a packet to be subject to priority control based on a first hash value calculated using the field value, determines a communication path of a transfer destination of a packet to be subject to load balancing control, to match a preset load balancing situation of the data buffer, based on a second hash value based on the first hash value, and transmits the packet to a data buffer corresponding to the destination virtual function and the communication path of the transfer destination.

Abstract: A packet processing apparatus includes a line adapter configured to receive packets from a communication line, a packet combining unit configured to generate a combined packet by combining a plurality of packets received from the communication line, a packet memory configured to store packets received from the communication line, and a combined packet transferring unit configured to DMA transfer the combined packet generated by the packet combining unit to the packet memory. The combined packet transferring unit determines an address of start data of each packet inside the combined packet on the packet memory, writes information on the address into the descriptor that is a predetermined data area on a memory, and DMA transfers the combined packet to the packet memory.

Abstract: A network load balancing apparatus has a data buffer provided to each communication path of transfer destinations of a received packet and being associated with a virtual function, determines a destination virtual function based on a field value of the received packet, determines a communication path of a transfer destination of a packet to be subject to priority control based on a first hash value calculated using the field value, determines a communication path of a transfer destination of a packet to be subject to load balancing control, to match a preset load balancing situation of the data buffer, based on a second hash value based on the first hash value, and transmits the packet to a data buffer corresponding to the destination virtual function and the communication path of the transfer destination.

Abstract: A network load balancing apparatus has a data buffer for each communication path of a received packet's transfer destinations, calculates a first hash value using a field value contained in the packet, determines, based on the field value of the packet or the first hash value, a communication path of a transfer destination of the packet subject to external transfer control for transmission to a predetermined external server, determines, based on the first hash value, a communication path of a transfer destination of the packet to be subject to priority control, determines, based on a second hash value based on the first hash value, a communication path of a transfer destination of the packet to be subject to load balancing control, to match a preset load balancing situation of the data buffer, and transmits the packet to a data buffer corresponding to the communication path of the transfer destination.

Abstract: A packet processing apparatus includes a line adapter configured to receive packets from a communication line, a packet combining unit configured to generate a combined packet by combining a plurality of packets received from the communication line, a packet memory configured to store packets received from the communication line, and a combined packet transferring unit configured to DMA transfer the combined packet generated by the packet combining unit to the packet memory. The combined packet transferring unit determines an address of start data of each packet inside the combined packet on the packet memory, writes information on the address into the descriptor that is a predetermined data area on a memory, and DMA transfers the combined packet to the packet memory.

Abstract: A packet processing device includes: a line adapter configured to receive packets from a communication line; a packet combining unit configured to generate a combined packet by combining a plurality of packets received from the communication line; a packet memory configured to store packets received from the communication line; and a combined packet transferring unit configured to DMA transfer the combined packet generated by the packet combining unit to the packet memory. The combined packet transferring unit writes information of an address of first data of each packet inside the combined packet on the packet memory into a descriptor that is a data area on a memory set in advance.

Abstract: A link control circuit (10) includes a plurality of hardware processing units serving as an uplink parser unit (11) configured to output, as an event, the contents of link control notified by an uplink control frame, a timer unit (12) configured to start/stop a timer and output a link event in accordance with expiration of the timer, a frame generation unit (13) configured to generate a downlink control frame containing the contents of link control, and a state management unit (15) configured to manage the state of the link in accordance with these events, and instruct the timer unit to start/stop the timer and the frame generation unit to generate the downlink control frame in accordance with the state of the link, thereby controlling connection establishment, maintenance, and disconnection of the link.

Abstract: An upstream allocation circuit (14) and a downstream allocation circuit (15) are provided in an OLT (1). For example, a superimposed frame obtained by bundling upstream frames (upstream control frames+upstream data frames) from all ONUS is input to the upstream allocation circuit (14) via a frame reproduction circuit (12-1). The superimposed frame may be generated at the stage of optical signals or generated after converting optical signals into electrical signals. The upstream allocation circuit (14) allocates each of the upstream control frames bundled into the superimposed frame to a predetermined PON control circuit (13) based on information (PON port number or LLID) added to the frames. The downstream allocation circuit (15) allocates, to a preset frame reproduction circuit (12), each downstream control frames output from the PON control circuits (13).

Abstract: A link control circuit (10) includes a plurality of hardware processing units serving as an uplink parser unit (11) configured to output, as an event, the contents of link control notified by an uplink control frame, a timer unit (12) configured to start/stop a timer and output a link event in accordance with expiration of the timer, a frame generation unit (13) configured to generate a downlink control frame containing the contents of link control, and a state management unit (15) configured to manage the state of the link in accordance with these events, and instruct the timer unit to start/stop the timer and the frame generation unit to generate the downlink control frame in accordance with the state of the link, thereby controlling connection establishment, maintenance, and disconnection of the link.

Abstract: A selection and distribution circuit (13) is provided between N optical transceivers (11) and one PON control circuit (12). The selection and distribution circuit (13) selects the optical transceiver (11) corresponding to an upstream frame that time-divisionally arrives, thereby transferring the upstream frame opto-electrically converted by the transceiver (11) to the PON control circuit (12) and distributing a downstream frame from the PON control circuit (12) to each optical transceiver (11). A power supply control circuit (23) stops power supply to at least one of one of optical transceivers (11) that are not used to transfer the frame of the optical transceivers (11) and a circuit that is not used to transfer the frame in the selection and distribution circuit (13). This can reduce the system cost per ONU in the optical transmission system.

Abstract: An upstream allocation circuit (14) and a downstream allocation circuit (15) are provided in an OLT (1). For example, a superimposed frame obtained by bundling upstream frames (upstream control frames+upstream data frames) from all ONUS is input to the upstream allocation circuit (14) via a frame reproduction circuit (12-1). The superimposed frame may be generated at the stage of optical signals or generated after converting optical signals into electrical signals. The upstream allocation circuit (14) allocates each of the upstream control frames bundled into the superimposed frame to a predetermined PON control circuit (13) based on information (PON port number or LLID) added to the frames. The downstream allocation circuit (15) allocates, to a preset frame reproduction circuit (12), each downstream control frames output from the PON control circuits (13).

Abstract: A selection and distribution circuit (13) is provided between N optical transceivers (11) and one PON control circuit (12). The selection and distribution circuit (13) selects the optical transceiver (11) corresponding to an upstream frame that time-divisionally arrives, thereby transferring the upstream frame opto-electrically converted by the transceiver (11) to the PON control circuit (12) and distributing a downstream frame from the PON control circuit (12) to each optical transceiver (11). A power supply control circuit (23) stops power supply to at least one of one of optical transceivers (11) that are not used to transfer the frame of the optical transceivers (11) and a circuit that is not used to transfer the frame in the selection and distribution circuit (13). This can reduce the system cost per ONU in the optical transmission system.