Patents by Inventor Salem Derisavi

Salem Derisavi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for performing register retiming in the presence of false path timing analysis exceptions
    Patent number: 10671781
    Abstract: A method for designing a system on a target device includes identifying a timing exception for a portion of a signal path. An area on the target device that includes components affected by the timing exception. Register retiming is performed where pipeline registers are added at boundaries of the area.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: June 2, 2020
    Assignee: Altera Corporation
    Inventors: Salem Derisavi, Gordon Raymond Chiu, Benjamin Gamsa, David Ian M. Milton
  • Method and apparatus for performing register retiming in the presence of timing analysis exceptions
    Patent number: 10339238
    Abstract: A method for designing a system on a target device includes identifying a timing exception for a portion of a signal path. An area on the target device that includes components affected by the timing exception. Constraints are generated that prevent registers residing in the area from being used for register retiming.
    Type: Grant
    Filed: June 17, 2017
    Date of Patent: July 2, 2019
    Assignee: Altera Corporation
    Inventors: Salem Derisavi, Gordon Raymond Chiu, Benjamin Gamsa
  • METHOD AND APPARATUS FOR PERFORMING REGISTER RETIMING IN THE PRESENCE OF FALSE PATH TIMING ANALYSIS EXCEPTIONS
    Publication number: 20180232475
    Abstract: A method for designing a system on a target device includes identifying a timing exception for a portion of a signal path. An area on the target device that includes components affected by the timing exception. Register retiming is performed where pipeline registers are added at boundaries of the area.
    Type: Application
    Filed: April 11, 2018
    Publication date: August 16, 2018
    Inventors: Salem DERISAVI, Gordon Raymond CHIU, Benjamin GAMSA, David Ian M. MILTON
  • Method and apparatus for performing register retiming in the presence of false path timing analysis exceptions
    Patent number: 9971858
    Abstract: A method for designing a system on a target device includes identifying a timing exception for a portion of a signal path. An area on the target device that includes components affected by the timing exception. Register retiming is performed where pipeline registers are added at boundaries of the area.
    Type: Grant
    Filed: February 20, 2015
    Date of Patent: May 15, 2018
    Assignee: Altera Corporation
    Inventors: Salem Derisavi, Gordon Raymond Chiu, Benjamin Gamsa, David Ian M. Milton
  • Method and Apparatus for Performing Register Retiming in the Presence of Timing Analysis Exceptions
    Publication number: 20170286590
    Abstract: A method for designing a system on a target device includes identifying a timing exception for a portion of a signal path. An area on the target device that includes components affected by the timing exception. Constraints are generated that prevent registers residing in the area from being used for register retiming.
    Type: Application
    Filed: June 17, 2017
    Publication date: October 5, 2017
    Inventors: Salem Derisavi, Gordon Raymond Chiu, Benjamin Gamsa
  • Method and apparatus for performing register retiming in the presence of timing analysis exceptions
    Patent number: 9710591
    Abstract: A method for designing a system on a target device includes identifying a timing exception for a portion of a signal path. An area on the target device that includes components affected by the timing exception. Constraints are generated that prevent registers residing in the area from being used for register retiming.
    Type: Grant
    Filed: February 20, 2015
    Date of Patent: July 18, 2017
    Assignee: Altera Corporation
    Inventors: Salem Derisavi, Gordon Raymond Chiu, Benjamin Gamsa
  • Intraprocedural privatization for shared array references within partitioned global address space (PGAS) languages
    Patent number: 8990791
    Abstract: Partitioned global address space (PGAS) programming language source code is retrieved by an executed PGAS compiler. At least one shared memory array access indexed by an affine expression that includes a distinct thread identifier that is constant and different for each of a group of program execution threads targeted to execute the PGAS source code is identified within the PGAS source code. It is determined whether the at least one shared memory array access results in a local shared memory access by all of the group of program execution threads for all references to the at least one shared memory array access during execution of a compiled executable of the PGAS source code. A direct memory access executable code is generated for each shared memory array access determined to result in the local shared memory access by all of the group of program execution threads.
    Type: Grant
    Filed: July 29, 2011
    Date of Patent: March 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Salem Derisavi, Ettore Tiotto
  • INTRAPROCEDURAL PRIVATIZATION FOR SHARED ARRAY REFERENCES WITHIN PARTITIONED GLOBAL ADDRESS SPACE (PGAS) LANGUAGES
    Publication number: 20140115276
    Abstract: Partitioned global address space (PGAS) programming language source code is retrieved by an executed PGAS compiler. At least one shared memory array access indexed by an affine expression that includes a distinct thread identifier that is constant and different for each of a group of program execution threads targeted to execute the PGAS source code is identified within the PGAS source code. It is determined whether the at least one shared memory array access results in a local shared memory access by all of the group of program execution threads for all references to the at least one shared memory array access during execution of a compiled executable of the PGAS source code. A direct memory access executable code is generated for each shared memory array access determined to result in the local shared memory access by all of the group of program execution threads.
    Type: Application
    Filed: July 29, 2011
    Publication date: April 24, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Salem Derisavi, Ettore Tiotto