Patents by Inventor Salil R. Raje
Salil R. Raje has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9864828Abstract: Implementing hardware accelerators using programmable integrated circuits may include performing, using a processor, a design flow on a static circuit design. The static circuit design may specify a region reserved for a hardware accelerator and a static region comprising interface circuitry configured to couple the hardware accelerator with an external node. The design flow may generate an implemented static circuit design. Metadata describing the interface circuitry may be generated using a processor. A device support archive including the implemented static circuit design and the metadata may be written, using the processor, to a computer readable storage medium.Type: GrantFiled: September 17, 2015Date of Patent: January 9, 2018Assignee: XILINX, INC.Inventors: Susheel Kumar Puthana, Stephen P. Rozum, Sudipto Chakraborty, David A. Knol, Yong Li, Fernando J. Martinez Vallina, Sonal Santan, Nabeel Shirazi, Salil R. Raje, Ethan T. Parker, Suman Kumar Timmireddy, Heera Nand
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Patent number: 7437695Abstract: A method of performing timing analysis on a circuit design for an integrated circuit (IC) can include selecting a physical portion of the IC that includes at least one instance of a logic hierarchy and generating a local timing constraint specific to the physical portion. The method also can include creating a software representation of the physical portion of the IC. The software representation can specify the local timing constraint and a shell netlist for the physical portion. The method further can include performing a timing analysis upon, at least part of, the circuit design using the software representation.Type: GrantFiled: April 5, 2005Date of Patent: October 14, 2008Assignee: Xilinx, Inc.Inventors: Abhishek Ranjan, David A. Knol, Salil R. Raje
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Patent number: 7370302Abstract: A method of partitioning a design across a plurality of integrated circuits can include creating a software construct for each one of the plurality of integrated circuits and assigning a plurality of instances to a selected software construct. Each of the plurality of instances can be from a different logic hierarchy. The method further can include automatically adding at least one input/output buffer and port to the selected software construct to accommodate the plurality of instances and creating nets connecting the plurality of instances and the at least one input/output buffer and port within the selected software construct.Type: GrantFiled: April 5, 2005Date of Patent: May 6, 2008Assignee: XILINX, Inc.Inventors: David A. Knol, Abhishek Ranjan, Salil R. Raje
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Patent number: 6961916Abstract: The present invention, generally speaking, provides a placement method for the physical design of integrated circuits in which natural topological feature clusters (topo-clusters) are discovered and exploited during the placement process. Topo-clusters may be formed based on various criteria including, for example, functional similarity, proximity (in terms of number of nets), and genus. Genus refers to a representation of a netlist in terms of a number of planar netlists—netlists in which no crossing of nets occurs. Topo-clusters drive initial placement, with all of the gates of a topo-cluster being placed initially in a single bin of the placement layout or within a group of positionally-related bins. The portion of a topo-cluster placed within a given bin is called a quanto-cluster. An iterative placement refinement process then follows, using a technique referred to herein as Geometrically-Bounded FM (GBFM), and in particular Dual GBFM.Type: GrantFiled: May 1, 2002Date of Patent: November 1, 2005Assignee: Synopsys, Inc.Inventors: Majid Sarrafzadeh, Lawrence Pileggi, Sharad Malik, Feroze Peshotan Taraporevala, Abhijeet Chakraborty, Gary K. Yeap, Salil R. Raje, Lilly Shieh, Douglas B. Boyle, Dennis Yamamoto
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Patent number: 6851099Abstract: The present invention, generally speaking, provides a placement method for the physical design of integrated circuits in which natural topological feature clusters (topo-clusters) are discovered and exploited during the placement process. Initial placement and placement refinement may be performed hierarchically using topocluster trees. A topocluster tree may be used to drive initial placement. An iterative placement refinement process then follows, using a technique referred to herein as Geometrically-Bounded FM (GBFM). In GBFM, FM is applied on a local basis to windows encompassing some number of bins. From iteration to iteration, windows may shift position and vary in size. When a region bounded by a window meets a specified cost threshold in terms of a specified cost function, that region does not participate. The cost function takes account of actual physical metrics-delay, area, congestion, power, etc.Type: GrantFiled: February 23, 2000Date of Patent: February 1, 2005Assignee: Synopsys, Inc.Inventors: Majid Sarrafzadeh, Salil R. Raje
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Patent number: 6775808Abstract: Methods and apparatus for a physical “sign-off” prototype tool that includes a prototype tool that generates a physical prototype for a design and a optimization tool that provides a designer with the option to further optimize the physical prototype before signing off on the design. In either situation, the “sign-off” prototype provides a forward prediction of the area, timing and performance of the final GDS of the design generated by a physical implementation tool.Type: GrantFiled: August 3, 2000Date of Patent: August 10, 2004Assignee: Monterey Design Systems, Inc.Inventors: Salil R. Raje, Lawrence T. Pileggi, Dinesh D. Gaitonde, Olivier R. Coudert, Padmini Gopalakrishnan, Jackson David Kreiter
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Publication number: 20020138816Abstract: The present invention, generally speaking, provides a placement method for the physical design of integrated circuits in which natural topological feature clusters (topo-clusters) are discovered and exploited during the placement process. Topo-clusters may be formed based on various criteria including, for example, functional similarity, proximity (in terms of number of nets), and genus. Genus refers to a representation of a netlist in terms of a number of planar netlists—netlists in which no crossing of nets occurs. Topo-clusters drive initial placement, with all of the gates of a topo-cluster being placed initially in a single bin of the placement layout or within a group of positionally-related bins. The portion of a topo-cluster placed within a given bin is called a quanto-cluster. An iterative placement refinement process then follows, using a technique referred to herein as Geometrically-Bounded FM (GBFM), and in particular Dual GBFM.Type: ApplicationFiled: May 1, 2002Publication date: September 26, 2002Inventors: Majid Sarrafzadeh, Lawrence Pileggi, Sharad Malik, Feroze Peshotan Taraporevala, Abhijeet Chakraborty, Gary K. Yeap, Salil R. Raje, Lilly Shieh, Douglas B. Boyle, Dennis Yamamoto
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Patent number: 6442743Abstract: The disclosure describes a placement method for the physical design of integrated circuits in which natural topological feature clusters are discovered and exploited during the placement process is disclosed. Topo-clusters drive initial placement, with all of the gates of a topo-cluster being placed initially in a single bin of the placement layout or within a group of positionally-related bins. An iterative placement refinement process is done using a technique referred to as Dual Geometrically-Bounded FM (GBFM). GBFM is applied on a local basis to windows encompassing a number of bins. From iteration to iteration, windows may shift position and vary in size. When a region bounded by a window meets a specified cost threshold in terms of a specified cost function, that region stops participating. Following the foregoing global placement process the circuit is then ready for detailed placement in which cells are assigned to placement rows.Type: GrantFiled: June 12, 1998Date of Patent: August 27, 2002Assignee: Monterey Design SystemsInventors: Majid Sarrafzadeh, Lawrence Pileggi, Sharad Malik, Feroze Peshotan Taraporevala, Abhijeet Chakraborty, Gary K. Yeap, Salil R. Raje, Lilly Shieh, Douglas B. Boyle, Dennis Yamamoto
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Patent number: 6286128Abstract: A method for design optimization using logical and physical information is provided. In one embodiment, a method for design optimization using logical and physical information, includes receiving a behavioral description of an integrated circuit or a portion of an integrated circuit, optimizing placement of circuit elements in accordance with a first cost function, and optimizing logic of the circuit elements in accordance with a second cost function, in which the optimizing placement of the circuit elements and the optimizing logic of the circuit elements are performed concurrently. The method can further include optimizing routing in accordance with a third cost function, in which the optimizing routing, the optimizing placement of the circuit elements, and the optimizing logic of the circuit elements are performed concurrently.Type: GrantFiled: June 12, 1998Date of Patent: September 4, 2001Assignee: Monterey Design Systems, Inc.Inventors: Lawrence Pileggi, Majid Sarrafzadeh, Sharad Malik, Abhijeet Chakraborty, Archie Li, Robert Eugene Shortt, Christopher Dunn, David Gluss, Dennis Yamamoto, Dinesh Gaitonde, Douglas B. Boyle, Emre Tuncer, Eric McCaughrin, Feroze Peshotan Taraporevala, Gary K. Yeap, James S. Koford, Joseph T. Rahmeh, Lilly Shieh, Salil R. Raje, Sam Jung Kim, Satamurthy Pullela, Yau-Tsun Steven Li, Tong Gao