Abstract: A floor planner tool for integrated circuit design which provides tools and displays for a designer to create a floor plan to define desired placement of circuits defined in a logical netlist by creating a physical hierarchy comprised of nested pblocks. Each pblock is a data structure which contains data which defines which circuits from the logical netlist are assigned to it. Each pblock stands alone and can be input to a place and route tool without the rest of the physical hierarchy. Each pblock data structure contains pointers to the circuits on the netlist assigned to that plbock, identifies other pblocks nested within it and contains at least a list of boundary pins for that pblock. Net data structures in the physical hierarchy define which nets are connected to which pins. PCellview data structures define the internal structure of each pblock.

Abstract: A floor planner tool for integrated circuit design which provides tools and displays for a designer to create a floor plan to define desired placement of circuits defined in a logical netlist by creating a physical hierarchy comprised of nested pblocks. Each pblock is a data structure which contains data which defines which circuits from the logical netlist are assigned to it. Each pblock stands alone and can be input to a place and route tool without the rest of the physical hierarchy. Each pblock data structure contains pointers to the circuits on the netlist assigned to that plbock, identifies other pblocks nested within it and contains a list of pins for the instances within the pblock. Net data structures in the physical hierarchy define which nets are connected to which pins.

Abstract: Progressively optimized clock tree/mesh construction is performed concurrently with placement of all remaining objects. Clock tree/mesh is specified loosely for initial placement, then followed by progressive detailed placement. In particular, preferred approach provides automated and reliable solution to clock tree/mesh construction, occuring concurrently with placement process so that clock tree wiring and buffering considers and influences placement and wiring of all other objects, such as logic gates, memory elements, macrocells, etc. Hence, in this concurrent manner, clock tree/mesh pre-wiring and pre-buffering may be based on construction of approximate clock tree using partitioning information only, i.e., prior to object placement. Further, present approach provides modified DME-based clock tree topology construction without meandering, and recursive algorithm for buffered clock tree construction.

Abstract: Method to optimize net lists used in the design and fabrication of integrated circuits by using simultaneous placement optimization, logic function optimization and net buffering algorithms. Method simultaneously obtains a placement of logic functions, mapping of logic functions on to library elements and buffering of nets connecting the logic functions.