Patents by Inventor Salvatore Rinaudo

Salvatore Rinaudo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for modeling large-area transistor devices, and computer program product therefor
    Patent number: 7788611
    Abstract: A method models the electrical characteristics of wide-channel transistors, such as power transistors, by generating a lumped-element distributed circuit model. More specifically, the active area of the transistor is organized in elementary transistor cells, which are substituted by active lumped elements. Similarly the passive area of the transistor is organized in elementary strip-lines, which are substituted by passive lumped elements. Preferably, the parameters of the lumped elements are extracted automatically from layout information, such as path dimensions, and technological data, such as sheet resistance of the metal layers, sheet resistance of the polysilicon layers and oxide thickness.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: August 31, 2010
    Assignee: STMicroelectronics S.r.l.
    Inventors: Tonio Gaetano Biondi, Giuseppe Greco, Salvatore Rinaudo, Gaetano Bazzano
  • METHOD FOR MODELING LARGE-AREA TRANSISTOR DEVICES, AND COMPUTER PROGRAM PRODUCT THEREFOR
    Publication number: 20080022246
    Abstract: A method models the electrical characteristics of wide-channel transistors, such as power transistors, by generating a lumped-element distributed circuit model. More specifically, the active area of the transistor is organized in elementary transistor cells, which are substituted by active lumped elements. Similarly the passive area of the transistor is organized in elementary strip-lines, which are substituted by passive lumped elements. Preferably, the parameters of the lumped elements are extracted automatically from layout information, such as path dimensions, and technological data, such as sheet resistance of the metal layers, sheet resistance of the polysilicon layers and oxide thickness.
    Type: Application
    Filed: June 28, 2007
    Publication date: January 24, 2008
    Applicant: STMICROELECTRONICS S.R.L.
    Inventors: Tonio Biondi, Giuseppe Greco, Salvatore Rinaudo, Gaetano Bazzano
  • MOS technology power device with low output resistance and low capacity, and related manufacturing process
    Publication number: 20020123195
    Abstract: A MOS-gated power device includes a plurality of elementary functional units, each elementary functional unit including a body region of a first conductivity type formed in a semiconductor material layer of a second conductivity type having a first resistivity value. Under each body region a respective lightly doped region of the second conductivity type is provided having a second resistivity value higher than the first resistivity value.
    Type: Application
    Filed: November 5, 2001
    Publication date: September 5, 2002
    Applicant: STMicroelectronics S.r.I
    Inventors: Ferruccio Frisina, Giuseppe Ferla, Salvatore Rinaudo
  • MOS technology power device with low output resistance and low capacitance, and related manufacturing process
    Patent number: 6228719
    Abstract: A MOS-gated power device includes a plurality of elementary functional units, each elementary functional unit including a body region of a first conductivity type formed in a semiconductor material layer of a second conductivity type having a first resistivity value. Under each body region a respective lightly doped region of the second conductivity type is provided having a second resistivity value higher than the first resistivity value.
    Type: Grant
    Filed: January 21, 1999
    Date of Patent: May 8, 2001
    Assignee: STMicroelectronics S.r.l.
    Inventors: Ferruccio Frisina, Giuseppe Ferla, Salvatore Rinaudo
  • MOS technology power device with low output resistance and low capacitance, and related manufacturing process
    Patent number: 5900662
    Abstract: A MOS-gated power device includes a plurality of elementary functional units, each elementary functional unit including a body region of a first conductivity type formed in a semiconductor material layer of a second conductivity type having a first resistivity value. Under each body region a respective lightly doped region of the second conductivity type is provided having a second resistivity value higher than the first resistivity value.
    Type: Grant
    Filed: November 4, 1996
    Date of Patent: May 4, 1999
    Assignees: SGS Thomson Microelectronics S.r.l., Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno
    Inventors: Ferruccio Frisina, Giuseppe Ferla, Salvatore Rinaudo