Abstract: A nonvolatile memory controller and a method for erase suspend management are disclosed. The nonvolatile memory controller includes an erase suspend circuit configured for determining a pre-suspend time each time that an erase operation of the nonvolatile memory device is suspended and for determining whether an erase-suspend limit has been reached using the determined pre-suspend time. The erase suspend circuit is further configured for incrementing the number of program and erase cycles when the erase-suspend limit has been reached.

Abstract: A nonvolatile memory controller and a method for erase suspend management are disclosed. The nonvolatile memory controller includes an erase suspend circuit configured for determining a pre-suspend time each time that an erase operation of the nonvolatile memory device is suspended and for determining whether an erase-suspend limit has been reached using the determined pre-suspend time. The erase suspend circuit is further configured for incrementing the number of program and erase cycles when the erase-suspend limit has been reached.

Abstract: A nonvolatile memory controller is disclosed that includes a read circuit configured to read memory cells of a nonvolatile memory device and a program and erase circuit configured to program and erase memory cells of the nonvolatile memory device. The nonvolatile memory controller includes a NAND shared algorithm circuit configured to communicate with the nonvolatile memory device so as to enter a test mode of the nonvolatile memory device and configured to modify the trim registers while the nonvolatile memory device is in the test mode such that the nonvolatile memory device performs one or more operations. The operations may include a suspendable program operation, a program suspend operation and an erase suspend operation.

Abstract: A nonvolatile memory controller and a method for erase suspend management are disclosed. The nonvolatile memory controller includes an erase suspend circuit configured for determining a pre-suspend time each time that an erase operation of the nonvolatile memory device is suspended and for determining whether an erase-suspend limit has been reached using the determined pre-suspend time. The erase suspend circuit is further configured for preventing subsequent suspends of the erase operation when the erase-suspend limit has been reached.

Abstract: A nonvolatile memory controller is disclosed that includes a read circuit configured to read memory cells of a nonvolatile memory device and a program and erase circuit configured to program and erase memory cells of the nonvolatile memory device. The nonvolatile memory controller includes a NAND shared algorithm circuit configured to communicate with the nonvolatile memory device so as to enter a test mode of the nonvolatile memory device and configured to modify the trim registers while the nonvolatile memory device is in the test mode such that the nonvolatile memory device performs one or more operations. The operations may include a suspendable program operation, a program suspend operation and an erase suspend operation.

Abstract: A nonvolatile memory controller and a method for erase suspend management are disclosed. The nonvolatile memory controller includes an erase suspend circuit configured for determining a pre-suspend time each time that an erase operation of the nonvolatile memory device is suspended and for determining whether an erase-suspend limit has been reached using the determined pre-suspend time. The erase suspend circuit is further configured for preventing subsequent suspends of the erase operation when the erase-suspend limit has been reached.

Abstract: A trimming structure for trimming functional parameters of an Integrated Circuit—IC—(100) includes a first (115a) and at least one second functional blocks (115b, . . . ,115n) with which a first (Vrg,a) and at least one second IC functional parameters (Vrg,b, . . . ,Vrg,n) are respectively associated. The trimming structure includes respective trimmable circuit structures (205a,210a, . . . ,205n,210n) included in the first and at least one second functional blocks, and trimming configuration storage (110) for storing trimming configurations for the trimmable circuit structures. A change in the trimming configuration of the first functional block causes a corresponding change in the trimming configuration of the second functional block.

Abstract: A device and method for programming an electrically programmable memory accesses a group of memory cells (MC1–MCk) of the memory to ascertain a programming state thereof (401,407;503,509a,513a); applies a programming pulse to those memory cells in the group whose programming state is not ascertained to correspond to a desired programming state (405;507a,509c,513c); and repeats the steps of accessing and applying for the memory cells in the group whose programming state is not ascertained (411;509b,513b). After the programming state of a prescribed number of memory cells in the group has been ascertained, the memory cells in the group are accessed again and the programming state of the memory cells whose programming state was previously ascertained is re-ascertained (413,415;515). At least one additional programming pulse is applied to those memory cells in the group whose programming state is not re-ascertained (405;507a,509c,513c).

Abstract: A trimming structure for trimming functional parameters of an Integrated Circuit—IC—(100) includes a first (115a) and at least one second functional blocks (115b, . . . ,115n) with which a first (Vrg,a) and at least one second IC functional parameters (Vrg,b, . . . ,Vrg,n) are respectively associated. The trimming structure includes respective trimmable circuit structures (205a,210a, . . . ,205n,210n) included in the first and at least one second functional blocks, and trimming configuration storage (110) for storing trimming configurations for the trimmable circuit structures. A change in the trimming configuration of the first functional block causes a corresponding change in the trimming configuration of the second functional block.

Abstract: Described herein is an erase method for an electrically erasable nonvolatile memory device, in particular an EEPROM-FLASH nonvolatile memory device, comprising a memory array formed by a plurality of memory cells arranged in rows and columns and grouped in sectors each formed by a plurality of subsectors, which are in turn formed by one or more rows. Erase of the memory array is performed by sectors and for each sector envisages applying an erase pulse to the gate terminals of all the memory cells of the sector, verifying erase of the memory cells of each subsector, and applying a further erase pulse to the gate terminals of the memory cells of only the subsectors that are not completely erased.

Abstract: A device and method for programming an electrically programmable memory accesses a group of memory cells (MC1-MCk) of the memory to ascertain a programming state thereof (401,407;503,509a,513a); applies a programming pulse to those memory cells in the group whose programming state is not ascertained to correspond to a desired programming state (405;507a,509c,513c); and repeats the steps of accessing and applying for the memory cells in the group whose programming state is not ascertained (411;509b,513b). After the programming state of a prescribed number of memory cells in the group has been ascertained, the memory cells in the group are accessed again and the programming state of the memory cells whose programming state was previously ascertained is re-ascertained (413,415;515). At least one additional programming pulse is applied to those memory cells in the group whose programming state is not re-ascertained (405;507a,509c,513c).

Abstract: Described herein is an erase method for an electrically erasable nonvolatile memory device, in particular an EEPROM-FLASH nonvolatile memory device, comprising a memory array formed by a plurality of memory cells arranged in rows and columns and grouped in sectors each formed by a plurality of subsectors, which are in turn formed by one or more rows. Erase of the memory array is performed by sectors and for each sector envisages applying an erase pulse to the gate terminals of all the memory cells of the sector, verifying erase of the memory cells of each subsector, and applying a further erase pulse to the gate terminals of the memory cells of only the subsectors that are not completely erased.