Abstract: An integrated circuit (IC) includes a package-integrated Faraday cage assembly to reduce the level of electromagnetic radiation emanating from the IC during operation. The IC uses a number of appropriately spaced leads on the IC package to form part of a Faraday cage surrounding a semiconductor chip within the IC. In one approach, the selected leads are coupled by a conductive member to a conductive cover plate of the IC package that forms an upper boundary of the Faraday cage. When the IC is installed in an external circuit, some or all of the selected leads are coupled together outside of the IC package (e.g., to an electrical ground) to form the lower boundary of the Faraday cage.

Abstract: According to an embodiment of the invention a circuit that is to be coupled to a reference voltage line. The circuit includes a noise coupling circuit that is to couple noise from the circuit to a reference voltage line based upon whether a driver is driving a data line.

Abstract: According to an embodiment of the invention a circuit that is to be coupled to a reference voltage line. The circuit includes a noise coupling circuit that is to couple noise from the circuit to a reference voltage line based upon whether a driver is driving a data line.

Abstract: A GTL I/O transceiver circuit having a pulsed latch receiver. A pulse generator generate a first pulse and a second pulse within the first pulse in response to a rising edge of the bus clock. The first pulse turns on the differential amplifier of the receiver circuit just long enough to provide a valid amplifier output signal. The second pulse controls a tristate latch such that the value of the amplifier output signal is latched before the differential amplifier is turned off. The pulsed latch receiver turns the differential amplifier on for only a fraction of the period of the bus clock such that power dissipation of the pulsed latch receiver circuit is significantly reduced. By using the pulsed latch receiver in VLSI components having hundreds of I/Os, significant reduction in overall component power dissipation can be achieved and static DC power is eliminated. The GTL I/O transceiver is useful for interfacing VLSI CMOS components to a terminated bus.

Abstract: A GTL I/O transceiver circuit having a pulsed latch receiver. A pulse generator generates a first pulse and a second pulse within the first pulse in response to a rising edge of the bus clock. The first pulse turns on the differential amplifier of the receiver circuit just long enough to provide a valid amplifier output signal. The second pulse controls a tristate latch such that the value of the amplifier output signal is latched before the differential amplifier is turned off. The pulsed latch receiver turns the differential amplifier on for only a fraction of the period of the bus clock such that power dissipation of the pulsed latch receiver circuit is significantly reduced. By using the pulsed latch receiver in VLSI components having hundreds of I/Os, significant reduction in overall component power dissipation can be achieved and static DC power is eliminated. The GTL I/O transceiver is useful for interfacing VLSI CMOS components to a terminated bus.