Patents by Inventor Sam G. Geha
Sam G. Geha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11784243Abstract: An embodiment of a semiconductor memory device including a multi-layer charge storing layer and methods of forming the same are described. Generally, the device includes a channel formed from a semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device; a tunnel oxide layer overlying the channel; and a multi-layer charge storing layer including an oxygen-rich, first oxynitride layer on the tunnel oxide layer in which a stoichiometric composition of the first oxynitride layer results in it being substantially trap free, and an oxygen-lean, second oxynitride layer on the first oxynitride layer in which a stoichiometric composition of the second oxynitride layer results in it being trap dense. In one embodiment, the device comprises a non-planar transistor including a gate having multiple surfaces abutting the channel, and the gate comprises the tunnel oxide layer and the multi-layer charge storing layer.Type: GrantFiled: December 2, 2021Date of Patent: October 10, 2023Assignee: LONGITUDE FLASH MEMORY SOLUTIONS LTDInventors: Sagy Charel Levy, Krishnaswamy Ramkumar, Fredrick Jenne, Sam G Geha
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Publication number: 20230017648Abstract: A semiconductor device including an oxide-nitride-oxide (ONO) structure having a multi-layer charge storing layer and methods of forming the same are provided. Generally, the method involves: (i) forming a first oxide layer of the ONO structure; (ii) forming a multi-layer charge storing layer comprising nitride on a surface of the first oxide layer; and (iii) forming a second oxide layer of the ONO structure on a surface of the multi-layer charge storing layer. Preferably, the charge storing layer comprises at least two silicon oxynitride layers having differing stoichiometric compositions of Oxygen, Nitrogen and/or Silicon. More preferably, the ONO structure is part of a silicon-oxide-nitride-oxide-silicon (SONOS) structure and the semiconductor device is a SONOS memory transistor. Other embodiments are also disclosed.Type: ApplicationFiled: September 15, 2022Publication date: January 19, 2023Inventors: Sagy Charel Levy, Krishnaswamy Ramkumar, Fredrick Jenne, Sam G. Geha
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Publication number: 20220093773Abstract: An embodiment of a semiconductor memory device including a multi-layer charge storing layer and methods of forming the same are described. Generally, the device includes a channel formed from a semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device; a tunnel oxide layer overlying the channel; and a multi-layer charge storing layer including an oxygen-rich, first oxynitride layer on the tunnel oxide layer in which a stoichiometric composition of the first oxynitride layer results in it being substantially trap free, and an oxygen-lean, second oxynitride layer on the first oxynitride layer in which a stoichiometric composition of the second oxynitride layer results in it being trap dense. In one embodiment, the device comprises a non-planar transistor including a gate having multiple surfaces abutting the channel, and the gate comprises the tunnel oxide layer and the multi-layer charge storing layer.Type: ApplicationFiled: December 2, 2021Publication date: March 24, 2022Inventors: Sagy Charel Levy, Krishnaswamy Ramkumar, Fredrick Jenne, Sam G Geha
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Patent number: 11222965Abstract: An embodiment of a semiconductor memory device including a multi-layer charge storing layer and methods of forming the same are described. Generally, the device includes a channel formed from a semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device; a tunnel oxide layer overlying the channel; and a multi-layer charge storing layer including an oxygen-rich, first oxynitride layer on the tunnel oxide layer in which a stoichiometric composition of the first oxynitride layer results in it being substantially trap free, and an oxygen-lean, second oxynitride layer on the first oxynitride layer in which a stoichiometric composition of the second oxynitride layer results in it being trap dense. In one embodiment, the device comprises a non-planar transistor including a gate having multiple surfaces abutting the channel, and the gate comprises the tunnel oxide layer and the multi-layer charge storing layer.Type: GrantFiled: December 24, 2019Date of Patent: January 11, 2022Assignee: LONGITUDE FLASH MEMORY SOLUTIONS LTDInventors: Sagy Charel Levy, Krishnaswamy Ramkumar, Fredrick Jenne, Sam G Geha
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Publication number: 20210249254Abstract: A semiconductor device including an oxide-nitride-oxide (ONO) structure having a multi-layer charge storing layer and methods of forming the same are provided. Generally, the method involves: (i) forming a first oxide layer of the ONO structure; (ii) forming a multi-layer charge storing layer comprising nitride on a surface of the first oxide layer; and (iii) forming a second oxide layer of the ONO structure on a surface of the multi-layer charge storing layer. Preferably, the charge storing layer comprises at least two silicon oxynitride layers having differing stochiometric compositions of Oxygen, Nitrogen and/or Silicon. More preferably, the ONO structure is part of a silicon-oxide-nitride-oxide-silicon (SONOS) structure and the semiconductor device is a SONOS memory transistor. Other embodiments are also disclosed.Type: ApplicationFiled: January 25, 2021Publication date: August 12, 2021Inventors: Sagy Charel Levy, Krishnaswamy Ramkumar, Fredrick Jenne, Sam G. Geha
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Patent number: 10903068Abstract: A semiconductor device including an oxide-nitride-oxide (ONO) structure having a multi-layer charge storing layer and methods of forming the same are provided. Generally, the method involves: (i) forming a first oxide layer of the ONO structure; (ii) forming a multi-layer charge storing layer comprising nitride on a surface of the first oxide layer; and (iii) forming a second oxide layer of the ONO structure on a surface of the multi-layer charge storing layer. Preferably, the charge storing layer comprises at least two silicon oxynitride layers having differing stochiometric compositions of Oxygen, Nitrogen and/or Silicon. More preferably, the ONO structure is part of a silicon-oxide-nitride-oxide-silicon (SONOS) structure and the semiconductor device is a SONOS memory transistor. Other embodiments are also disclosed.Type: GrantFiled: April 14, 2016Date of Patent: January 26, 2021Assignee: LONGITUDE FLASH MEMORY SOLUTIONS LTD.Inventors: Sagy Charel Levy, Krishnaswamy Ramkumar, Fredrick Jenne, Sam G. Geha
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Publication number: 20200144399Abstract: An embodiment of a semiconductor memory device including a multi-layer charge storing layer and methods of forming the same are described. Generally, the device includes a channel formed from a semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device; a tunnel oxide layer overlying the channel; and a multi-layer charge storing layer including an oxygen-rich, first oxynitride layer on the tunnel oxide layer in which a stoichiometric composition of the first oxynitride layer results in it being substantially trap free, and an oxygen-lean, second oxynitride layer on the first oxynitride layer in which a stoichiometric composition of the second oxynitride layer results in it being trap dense. In one embodiment, the device comprises a non-planar transistor including a gate having multiple surfaces abutting the channel, and the gate comprises the tunnel oxide layer and the multi-layer charge storing layer.Type: ApplicationFiled: December 24, 2019Publication date: May 7, 2020Inventors: Sagy Charel Levy, Krishnaswamy Ramkumar, Fredrick Jenne, Sam G. Geha
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Publication number: 20160300724Abstract: A semiconductor device including an oxide-nitride-oxide (ONO) structure having a multi-layer charge storing layer and methods of forming the same are provided. Generally, the method involves: (i) forming a first oxide layer of the ONO structure; (ii) forming a multi-layer charge storing layer comprising nitride on a surface of the first oxide layer; and (iii) forming a second oxide layer of the ONO structure on a surface of the multi-layer charge storing layer. Preferably, the charge storing layer comprises at least two silicon oxynitride layers having differing stochiometric compositions of Oxygen, Nitrogen and/or Silicon. More preferably, the ONO structure is part of a silicon-oxide-nitride-oxide-silicon (SONOS) structure and the semiconductor device is a SONOS memory transistor. Other embodiments are also disclosed.Type: ApplicationFiled: April 14, 2016Publication date: October 13, 2016Inventors: Sagy Charel Levy, Krishnaswamy Ramkumar, Fredrick Jenne, Sam G. Geha
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Patent number: 9355849Abstract: A semiconductor device including an oxide-nitride-oxide (ONO) structure having a multi-layer charge storing layer and methods of forming the same are provided. Generally, the method involves: (i) forming a first oxide layer of the ONO structure; (ii) forming a multi-layer charge storing layer comprising nitride on a surface of the first oxide layer; and (iii) forming a second oxide layer of the ONO structure on a surface of the multi-layer charge storing layer. Preferably, the charge storing layer comprises at least two silicon oxynitride layers having differing stochiometric compositions of Oxygen, Nitrogen and/or Silicon. More preferably, the ONO structure is part of a silicon-oxide-nitride-oxide-silicon (SONOS) structure and the semiconductor device is a SONOS memory transistor. Other embodiments are also disclosed.Type: GrantFiled: June 13, 2013Date of Patent: May 31, 2016Assignee: CYPRESS SEMICONDUCTOR CORPORATIONInventors: Sagy Charel Levy, Krishnaswamy Ramkumar, Fredrick B. Jenne, Sam G. Geha
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Patent number: 9349824Abstract: A method of fabricating a memory device is described. Generally, the method includes: forming a tunneling layer on a substrate; forming on the tunneling layer a multi-layer charge storing layer including at least a first charge storing layer comprising an oxygen-rich oxynitride overlying the tunneling layer, and a second charge storing layer overlying the first charge storing layer comprising a silicon-rich and nitrogen-rich oxynitride layer that is oxygen-lean relative to the first charge storing layer and comprises a majority of charge traps distributed in the multi-layer charge storing layer; and forming a blocking layer on the second oxynitride layer; and forming a gate layer on the blocking layer. Other embodiments are also described.Type: GrantFiled: February 4, 2014Date of Patent: May 24, 2016Assignee: CYPRESS SEMICONDUCTOR CORPORATIONInventors: Sagy Charel Levy, Krishnaswamy Ramkumar, Frederick B. Jenne, Sam G Geha
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Publication number: 20140284696Abstract: A method of fabricating a memory device is described. Generally, the method includes: forming a tunneling layer on a substrate; forming on the tunneling layer a multi-layer charge storing layer including at least a first charge storing layer comprising an oxygen-rich oxynitride overlying the tunneling layer, and a second charge storing layer overlying the first charge storing layer comprising a silicon-rich and nitrogen-rich oxynitride layer that is oxygen-lean relative to the first charge storing layer and comprises a majority of charge traps distributed in the multi-layer charge storing layer; and forming a blocking layer on the second oxynitride layer; and forming a gate layer on the blocking layer. Other embodiments are also described.Type: ApplicationFiled: February 4, 2014Publication date: September 25, 2014Applicant: Cypress Semiconductor CorporationInventors: Sagy Charel Levy, Krishnaswamy Ramkumar, Frederick B. Jenne, Sam G. Geha
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Patent number: 6627547Abstract: The invention enables a layer of metal to be formed on a substrate with few or no voids formed in the layer, with increased throughput and without raising the temperature of the substrate to a level that may damage the substrate. A layer of metal can be formed on a substrate using a cold deposition step followed by a hot deposition step. The cold deposition step need only be performed for a time sufficient to deposit metal over the entire surface on which the metal layer is to be formed. In the hot deposition step, further metal is deposited while the substrate is rapidly heated to a target temperature. The rapid heating quickly mobilizes the atoms of the deposited metal, making the deposited metal far less susceptible to cusping and voiding than has been the case with previous methods for depositing a metal layer on a substrate that include a cold deposition step followed by a hot deposition step.Type: GrantFiled: May 29, 2001Date of Patent: September 30, 2003Assignee: Cypress Semiconductor CorporationInventor: Sam G. Geha
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Patent number: 6534398Abstract: A method of forming metallic layers on a substrate includes the steps of forming a first layer including a first metal on the substrate; cooling the first layer for a period of time sufficient to suppress formation of an intermetallic phase; and forming a second layer including a second metal distinct from the first metal on the first layer. The cooling step decreases the roughness of the resultant stacked structure by suppressing the formation of an intermetallic phase layer between the two metallic layers and by suppressing “bumps” or other surface irregularities that may form at relatively reactive grain boundaries in the first layer.Type: GrantFiled: January 12, 2001Date of Patent: March 18, 2003Assignee: Cypress Semiconductor Corp.Inventors: Ende Shan, Gorley Lau, Sam G. Geha
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Publication number: 20010036717Abstract: The invention enables a layer of metal to be formed on a substrate with few or no voids formed in the layer, with increased throughput and without raising the temperature of the substrate to a level that may damage the substrate. A layer of metal can be formed on a substrate using a cold deposition step followed by a hot deposition step. The cold deposition step need only be performed for a time sufficient to deposit metal over the entire surface on which the metal layer is to be formed. In the hot deposition step, further metal is deposited while the substrate is rapidly heated to a target temperature. The rapid heating quickly mobilizes the atoms of the deposited metal, making the deposited metal far less susceptible to cusping and voiding than has been the case with previous methods for depositing a metal layer on a substrate that include a cold deposition step followed by a hot deposition step.Type: ApplicationFiled: May 29, 2001Publication date: November 1, 2001Inventor: Sam G. Geha
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Patent number: 6309971Abstract: The invention enables a layer of metal to be formed on a substrate with few or no voids formed in the layer, with increased throughput and without raising the temperature of the substrate to a level that may damage the substrate. A layer of metal can be formed on a substrate using a cold deposition step followed by a hot deposition step. The cold deposition step need only be performed for a time sufficient to deposit metal over the entire surface on which the metal layer is to be formed. In the hot deposition step, further metal is deposited while the substrate is rapidly heated to a target temperature. The rapid heating quickly mobilizes the atoms of the deposited metal, making the deposited metal far less susceptible to cusping and voiding than has been the case with previous methods for depositing a metal layer on a substrate that include a cold deposition step followed by a hot deposition step.Type: GrantFiled: August 1, 1996Date of Patent: October 30, 2001Assignee: Cypress Semiconductor CorporationInventor: Sam G. Geha
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Publication number: 20010008793Abstract: A method of forming metallic layers on a substrate includes the steps of forming a first layer including a first metal on the substrate; cooling the first layer for a period of time sufficient to suppress formation of an intermetallic phase; and forming a second layer including a second metal distinct from the first metal on the first layer. The cooling step decreases the roughness of the resultant stacked structure by suppressing the formation of an intermetallic phase layer between the two metallic layers and by suppressing “bumps” or other surface irregularities that may form at relatively reactive grain boundaries in the first layer.Type: ApplicationFiled: January 12, 2001Publication date: July 19, 2001Applicant: Cypress Semiconductor Corp.Inventors: Ende Shan, Gorley Lau, Sam G. Geha
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Patent number: 6187667Abstract: A method of forming metallic layers on a substrate includes the steps of forming a first layer including a first metal on the substrate; cooling the first layer for a period of time sufficient to suppress formation of an intermetallic phase; and forming a second layer including a second metal distinct from the first metal on the first layer. The cooling step decreases the roughness of the resultant stacked structure by suppressing the formation of an intermetallic phase layer between the two metallic layers and by suppressing “bumps” or other surface irregularities that may form at relatively reactive grain boundaries in the first layer.Type: GrantFiled: June 17, 1998Date of Patent: February 13, 2001Assignee: Cypress Semiconductor Corp.Inventors: Ende Shan, Gorley Lau, Sam G. Geha
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Patent number: 6156645Abstract: A wetting layer is formed on a substrate at a relatively high process temperature (e.g., the temperature of the substrate and/or the temperature within a process chamber in which the wetting layer is formed). A metallization layer that is subsequently formed on the wetting layer adheres to the wetting layer better than the metallization layer would adhere to the wetting layer if the wetting layer was formed at a lower process temperature. The high process temperature causes the density of the wetting layer to be increased, so that, consequently, the wetting layer has a smoother surface to which the metallization layer can adhere.Type: GrantFiled: October 25, 1996Date of Patent: December 5, 2000Assignee: Cypress Semiconductor CorporationInventors: Sam G. Geha, Ende Shan
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Patent number: 5339039Abstract: A Langmuir probe system for measuring plasma internal discharge parameters in a radio frequency excited plasma processing system includes an electrically tuned resonant circuit. The electrically tuned resonant circuit includes a semiconductor variable capacitor. Specifically, an inductor and FET are connected in parallel to form a resonant circuit used to electrically tune the Langmuir probe. The tuning circuit is placed within a moveable, electrically floating, probe housing and is electrically tuned to improve tuning accuracy and to reduce detuning during operation.Type: GrantFiled: September 29, 1992Date of Patent: August 16, 1994Assignee: Arizona Board of Regents on behalf of the University of ArizonaInventors: Robert N. Carlile, Sam G. Geha