Abstract: A non-volatile memory system includes an SRAM and a backup store of E.sup.2 PROMs. In the event of a short duration power interruption, the memory system enters a hold mode in which data maintenance power is supplied to the SRAM by discharging a backup capacitor, and accessing of the SRAM by a host computer is halted. If the backup capacitor voltage does not fall below a threshold before power is restored, the hold mode is terminated and accessing by the host computer continues. If the backup capacitor voltage falls below the threshold, operating power is supplied to the SRAM, E.sup.2 PROM, and associated circuitry to download all data and row and column parity data into the E.sup.2 PROM by further discharging of the backup capacitor. Row parity and column parity information are accumulated by a bit-per-chip accumulation technique that allows convenient error correction on a "per chip" basis. Data is encrypted and decrypted on the basis of a fully erasable magnetic key.

Abstract: The sense voltages of an NDRO core memory including two cores per memory bit are increased by using a "soft write" technique wherein one of the two ferrite cores of each memory bit is written into by a smaller write current than the other. This results in a steeper slope toward the knee of the lower part of the hysteresis characteristic of the first core. The steeper slope results in a larger induced voltage for the first core. This increases the difference between the induced voltages of the two cores, thereby increasing the sense voltage to be detected by the sense circuitry.

Abstract: A core memory system includes a plurality of word lines strung through a core memory array and a plurality of field effect transistors coupling respective ones of the word select lines to an address decoding circuit. In one embodiment of the invention, the field effect transistors are utilized in conjunction with a transformer selection system. In the transformer selection system, the drain electrodes of each field effect transistor are connected in series with respective ones of a plurality of secondary windings of a transformer. The system includes a plurality of such transformers, the primary windings of the various transformers being selected in response to a first decoder. The gates of the respective field effect transistors are selected in response to a second decoder.