Abstract: Techniques are disclosed for non-planar transistors having varying channel widths (Wsi). In some instances, the resulting structure has a fin (or nanowires, nanoribbons, or nanosheets) comprising a first channel region and a second channel region, with a source or drain region between the first channel region and the second channel region. The widths of the respective channel regions are independent of each other, e.g., a first width of the first channel region is different from a second width of the second channel region. The variation in width of a given fin structure may vary in a symmetric fashion or an asymmetric fashion. In an embodiment, a spacer-based forming approach is utilized that allows for abrupt changes in width along a given fin. Sub-resolution fin dimensions are achievable as well.

Abstract: Techniques are disclosed for non-planar transistors having varying channel widths (Wsi). In some instances, the resulting structure has a fin (or nanowires, nanoribbons, or nanosheets) comprising a first channel region and a second channel region, with a source or drain region between the first channel region and the second channel region. The widths of the respective channel regions are independent of each other, e.g., a first width of the first channel region is different from a second width of the second channel region. The variation in width of a given fin structure may vary in a symmetric fashion or an asymmetric fashion. In an embodiment, a spacer-based forming approach is utilized that allows for abrupt changes in width along a given fin. Sub-resolution fin dimensions are achievable as well.

Abstract: Systems and techniques relating to the layout and use of sub-resolution assist features. In one implementation, a mask includes a first feature and a second feature separated from each other by a gap and a sub-resolution assist feature bridging the gap between the first feature and the second feature.

Abstract: Systems and techniques relating to the layout and use of sub-resolution assist features. In one implementation, a mask includes a first feature and a second feature separated from each other by a gap and a sub-resolution assist feature bridging the gap between the first feature and the second feature.

Abstract: Diagonal corner-to-corner sub-resolution assist features for use in photolithography are described. The diagonal features may be applied to one or a group of main features. Such features may be developed starting by synthesizing a photolithography mask having a first feature aligned along a linear axis and having a corner and a second feature aligned along a linear axis and having a corner, the corners of first and second features being separated from each other by a gap. The features may be developed by determining at least one diagonal line between the corners of the features to bridge the gap between the corners, applying a sub-resolution assist feature along the determined line, and modifying the synthesized photolithography mask to include the sub-resolution assist feature.

Abstract: Systems and techniques relating to the layout and use of sub-resolution assist features. In one implementation, a mask includes a first feature and a second feature separated from each other by a gap and a sub-resolution assist feature bridging the gap between the first feature and the second feature.

Abstract: Method for using chromeless phase shift lithography (CPL) masks to pattern contacts on semiconductor substrates and corresponding CPL masks for performing the method. The method for patterning contacts includes illuminating a CPL mask comprising a reticle having a plurality of phase-shifting features interspersed with non-phase-shifting areas using a short wavelength UV light source, wherein the phase-shifting features are configured in a pattern corresponding to a target pattern of the contacts on the semiconductor substrate. Phase-shifted and non-phase-shifted light passing through the reticle are projected as an aerial image onto a layer of a negative tone resist applied over the semiconductor substrate to pattern the contacts in the resist. The phase-shifting features are recesses which cause light passing therethrough to be phase-shifted by approximately 180° from light passing through non-phase-shifting areas of the mask.

Abstract: Systems and techniques for accommodating diffraction in the printing of features on a substrate. In one implementation, a method includes identifying a pair of features to be printed using a corresponding pair of patterning elements and increasing a separation distance between the pair of patterning elements while maintaining the sufficiently small pitch between the corresponding imaged features. The pitch of the pair of features can be sufficiently small that, upon printing, diffraction will make a separation between the features smaller than a separation between the corresponding pair of patterning elements.

Abstract: Diagonal corner-to-corner sub-resolution assist features for use in photolithography are described. The diagonal features may be applied to one or a group of main features. Such features may be developed starting by synthesizing a photolithography mask having a first feature aligned along a linear axis and having a corner and a second feature aligned along a linear axis and having a corner, the corners of first and second features being separated from each other by a gap. The features may be developed by determining at least one diagonal line between the corners of the features to bridge the gap between the corners, applying a sub-resolution assist feature along the determined line, and modifying the synthesized photolithography mask to include the sub-resolution assist feature.

Abstract: A chromeless phase shift lithography (CPL) mask is described herein. The CPL mask includes a reticle having a phase-shifting feature pattern to produce a projected aerial image for patterning one or more large resist areas on a semiconductor substrate. The phase-shifting feature pattern includes an inner pattern comprising a plurality of phase-shifting features interspersed with non-phase-shifting areas. The phase-shifting features and the non-phase-shifting areas are arranged in a substantially alternating two-dimensional pattern surrounded by a substantially-filled phase-shifting peripheral area having a perimeter forming a pattern outline that is similar to an outline of the one or more large resist areas. Light that passes through the phase-shifting features and the phase-shifting peripheral area is phase-shifted by approximately 180 degrees from light passing through the non-phase-shifting areas of the CPL mask.

Abstract: Method for using chromeless phase shift lithography (CPL) masks to pattern large line/space geometries. The method comprises using light at a wavelength of one of 248 nm, 193 nm, or 157 nm to illumimate a CPL mask comprising a reticle having a plurality of phase-shifting features interspersed with non-phase-shifting areas arranged in a substantially alternating two-dimensional pattern. When light passes through the phase-shifting features it is phase-shifted relative to light passing through the non-phase-shifting areas of the CPL mask. The phase-shifted light and non-phase-shifted light passing through the reticle are then projected onto a resist layer applied over a semiconductor substrate. The resultant composite aerial image intensity distribution is such that an area of the resist having a shape defined by a periphery of a corresponding pattern of phase-shifting features is sufficiently exposed to pattern a large area feature in the resist.

Abstract: Method for using chromeless phase shift lithography (CPL) masks to pattern large line/space geometries and corresponding CPL masks. The method comprises using a short wavelength light to illuminate a CPL mask comprising a reticle having a plurality of phase-shifting features interspersed with non-phase-arranged in a substantially alternating two-dimensional pattern. When light passes through the phase-shifting features it is phase-shifted relative to light passing through the non-phase-shifting areas of the CPL mask. The phase-shifted and non-phase-shifted light passing through the reticle is then projected onto a resist layer applied over a semiconductor substrate. The resultant composite aerial image intensity distribution is such that an area of the resist having a shape defined by a periphery of a corresponding pattern of phase-shifting features is sufficiently exposed to pattern a large area feature in the resist.

Abstract: A mask pattern may be decomposed into two or more masks, each having a pitch greater than that of the original mask pattern. New, “partial-pattern” masks may be created for each of the new mask patterns. The original mask pattern is transferred to the photoresist for the corresponding layer using a multiple exposure technique in which the photoresist is exposed with each of the partial-pattern masks individually, e.g., back-to-back in a pass through a scanner, to define all of the features in the original pattern.

Abstract: A method of integrating a polymeric interlayer dielectric. The method comprises forming a dielectric layer comprising a polymer on a conductive layer formed on a substrate. A sacrificial hard mask is then formed on the dielectric layer. A first photoresist layer is then patterned on the sacrificial hard mask to define a first etched region, which is formed through the dielectric layer while substantially all of the first photoresist layer is removed. A sacrificial fill layer then covers the sacrificial hard mask and fills the first etched region. A second photoresist layer is patterned over the sacrificial fill layer to define a second etched region which is formed through the sacrificial fill layer and the dielectric layer while substantially all of the second photoresist layer and the sacrificial fill layer are simultaneously removed.

Abstract: Method for using chromeless phase shift lithography (CPL) masks to pattern large line/space geometries and corresponding CPL masks. The method comprises using a short wavelength light to illuminate a CPL mask comprising a reticle having a plurality of phase-shifting features interspersed with non-phase-arranged in a substantially alternating two-dimensional pattern. When light passes through the phase-shifting features it is phase-shifted relative to light passing through the non-phase-shifting areas of the CPL mask. The phase-shifted and non-phase-shifted light passing through the reticle is then projected onto a resist layer applied over a semiconductor substrate. The resultant composite aerial image intensity distribution is such that an area of the resist having a shape defined by a periphery of a corresponding pattern of phase-shifting features is sufficiently exposed to pattern a large area feature in the resist.

Abstract: A method of integrating a polymeric interlayer dielectric. The method comprises forming a dielectric layer comprising a polymer on a conductive layer formed on a substrate. A sacrificial hard mask is then formed on the dielectric layer. A first photoresist layer is then patterned on the sacrificial hard mask to define a first etched region, which is formed through the dielectric layer while substantially all of the first photoresist layer is removed. A sacrificial fill layer then covers the sacrificial hard mask and fills the first etched region. A second photoresist layer is patterned over the sacrificial fill layer to define a second etched region which is formed through the sacrificial fill layer and the dielectric layer while substantially all of the second photoresist layer and the sacrificial fill layer are simultaneously removed.

Abstract: A method of forming an interconnection including the steps of depositing a first masking material over a first conductive region of an integrated circuit substrate and depositing a dielectric material over the first masking material. The method also includes forming a via through the dielectric material to expose the first masking material and a second masking material is deposited in a portion of the via. A trench is formed in the dielectric material over a portion of the via and the second masking material is removed from the via. The via is then extended through the first masking material and a conductive material is deposited in the via.

Abstract: A method of forming an interconnection including the steps of forming a sacrificial material that comprises a physical property that is generally insensitive to a photo-reaction in a via through a dielectric material to a masking material over a conductive material. The method also includes forming a trench over in the dielectric material over the via and removing the sacrificial material from the via.

Abstract: A single step electroplating process for interconnect via fill and metal line formation on a semiconductor substrate is disclosed. In this process, a barrier layer is formed onto a surface of a substrate that has at least one via and then a conductive layer is formed onto the barrier layer. Next, a photoresist layer is applied and patterned on top of the conductive layer. The via plugs and metal lines are then deposited on the substrate simultaneously using an electroplating process. After the electroplating process is completed, the photoresist and the conductive layer between the deposited metal lines are removed. The process provides a simple, economical and highly controllable means of forming metal interconnect systems while avoiding the difficulties associated with depositing and patterning metal by traditional semiconductor fabrication techniques.

Abstract: An improved method of forming an integrated circuit, which includes forming a conductive layer on a substrate, then forming a dielectric layer on the conductive layer. After forming the dielectric layer, a layer of photoresist is patterned to define a region to be etched. A first etched region is then formed by removing a first portion of the dielectric layer. That first etched region is filled with a preferably light absorbing sacrificial material having dry etch properties similar to those of the dielectric layer. A second etched region is then formed by removing the sacrificial material and a second portion of the dielectric layer. This improved method may be used to make an integrated circuit that includes a dual damascene interconnect.