Abstract: The present invention is directed to a memory data interface for transferring data between a memory device and an integrated circuit, whereby, in accordance with one aspect of the present invention, the memory data interface includes a data selector for selecting and normalizing data from memory devices operating at different data transfer timing, and, in accordance with another aspect of the present invention, the memory data interface is capable of transferring data between a memory device and an integrated circuit having a different bus width than the memory device. In accordance with yet another aspect of the present invention, the memory data interface is capable of transferring data between an integrated circuit and a variety of different memory device having different data bus widths.

Abstract: In an embodiment, an initialization extension device may provide an extended initialization period to enable a processor to configure a device, for example, an application specific integrated circuit (ASIC), prior to entering an operating mode. The device may include a number of control registers that may be configured to default settings in a register initialization period commenced in response to a reset signal. The reset signal may also trigger an extension timer to countdown a timer extended initialization period. During the timer extended initialization period, the processor may write an extension control signal, e.g., an extension bit, to a register. An initialization extension unit may maintain the device in an initialization mode during the timer extended initialization period and/or while the register contains the extension control signal. The processor may configure the control registers for one or more operations the device may perform when it enters the operating mode.

Abstract: In an embodiment, an initialization extension device may provide an extended initialization period to enable a processor to configure a device, for example, an application specific integrated circuit (ASIC), prior to entering an operating mode. The device may include a number of control registers that may be configured to default settings in a register initialization period commenced in response to a reset signal. The reset signal may also trigger an extension timer to countdown a timer extended initialization period. During the timer extended initialization period, the processor may write an extension control signal, e.g., an extension bit, to a register. An initialization extension unit may maintain the device in an initialization mode during the timer extended initialization period and/or while the register contains the extension control signal. The processor may configure the control registers for one or more operations the device may perform when it enters the operating mode.

Abstract: A hub port in a Fiber Channel loop includes a hub data source, a loop initialization data detect circuit, and a loop initialization counter. The hub data source supplies data to the hub port from the Fiber Channel loop. The loop initialization data detect circuit is configured to detect valid loop initialization sequences from an attached node port and the hub data source. The loop initialization counter is configured to increment a count value of the valid loop initialization sequence from the attached node port if the loop initialization sequence from the node port does not match the valid loop initialization sequence from the hub data source. This state indicates that the loop initialization sequence is initiated by the attached node port.

Abstract: A system with a first random access memory (RAM), a second RAM, a first processor coupled to the first RAM and a second processor coupled to the second RAM. The first RAM is configured to store input/output (I/O) completions from at least two engines. The second RAM is also configured to store I/O completions from at least two engines. When all engines are active, the system writes I/O completions from the engines to the first and second RAMs. The first processor processes I/O completions stored in the first RAM. The second processor processes I/O completions stored in the second RAM.

Abstract: A hub port in a Fibre Channel loop for detecting and bypassing attached node ports in an OLD-PORT state is disclosed. The hub port includes a hub data source, a detect circuits, and an output control circuit. The hub data source supplies data to the hub port from a Fibre Channel loop. The detect circuit is configured to detect a valid non-Arbitrated Loop sequence from an attached node port indicating that the node port is in an OLD-PORT state. The output control circuit operates to bypass the node port from the loop when the valid non-Arbitrated Loop sequence is detected.

Abstract: A hub port in a loop network is disclosed. The hub port includes a hub data source, first and second detect circuits, and a processor. The hub data source supplies data to the hub port from the loop network. The first detect circuit is configured to detect a first sequence from an attached node port establishing a loop circuit. The second sequence from the attached node port indicates to terminate the loop circuit. The processor is configured to receive the first sequence from the first detect circuit. Further, the processor operates to close a detect window and to increment a sequence origination count, if the detect window is open. The second detect circuit is configured to detect the second sequence from the hub data source confirming the termination of the loop circuit.

Abstract: In an embodiment, an initialization extension device may provide an extended initialization period to enable a processor to configure a device, for example, an application specific integrated circuit (ASIC), prior to entering an operating mode. The device may include a number of control registers that may be configured to default settings in a register initialization period commenced in response to a reset signal. The reset signal may also trigger an extension timer to countdown a timer extended initialization period. During the timer extended initialization period, the processor may write an extension control signal, e.g., an extension bit, to a register. An initialization extension unit may maintain the device in an initialization mode during the timer extended initialization period and/or while the register contains the extension control signal. The processor may configure the control registers for one or more operations the device may perform when it enters the operating mode.

Abstract: A hub port in a Fibre Channel loop for detecting and bypassing attached node ports in an OLD-PORT state is disclosed. The hub port includes a hub data source, a detect circuits, and an output control circuit. The hub data source supplies data to the hub port from a Fibre Channel loop. The detect circuit is configured to detect a valid non-Arbitrated Loop sequence from an attached node port indicating that the node port is in an OLD-PORT state. The output control circuit operates to bypass the node port from the loop when the valid non-Arbitrated Loop sequence is detected.

Abstract: A "virtual FIFO" system for use in buffering data between transacting buses that transfer data at different rates includes a memory device and a controller that partitions the memory device into multiple regions, each of which is configured to operate as a distinct data buffer.

Abstract: An elastic bus interface receives and registers an external data transfer signal and generates an internal data transfer signal that always begins at the beginning of the subsequent clock cycle regardless of the time of arrival of the external data transfer signal. By employing a plurality of data output registers in a pipeline and using only the internal data transfer signal, data is fed to a bus so as to ensure that almost a complete clock cycle is available for setup time to accomplish data transfer. The invention can operate with high speed buses using only simple conventional circuitry and modest process geometries requiring only minimal chip area and power.

Abstract: A system for changing the source and destination devices of data transfers under software control. Default data transfers are made from numbered source devices to the same-numbered destination devices, the data requests being routed through multiplexers which pair, for example, source 1 with destination 1, source 2 with destination 2, etc. The multiplexer control signals originate in a register which is originally loaded with default control bits. However, in real time, the bits within the control register can be re-loaded to provide outputs other than the default values. Then, the data from a source can be directed to any one of the destination devices.

Abstract: A circuit for enabling data transfer between one data bus connected to a number of devices, such as accelerator cards, and a second data bus, such as one found in a computer. The two data busses are connected by a number of FIFO buffers, and an arbitrator selects a source and destination for each packet. The circuit allows the computer to freeze the data in any or all buffers so that it can be inspected and changed if necessary, but only after the entire current packet for the selected buffer or buffers has been transferred.