Abstract: Performing a built-in self-test (BIST) on a memory macro includes generating a plurality of input vectors such that at least one input vector of the plurality of input vectors is transmitted to the memory macro in each of a plurality of cycles, receiving in each of the plurality of cycles, an output data from the memory macro. The output data is generated by the memory macro in response to processing the at least one input vector. The BIST also includes comparing the output data in each of the plurality of cycles with a signature value and determining whether the memory macro is normal or faulty based upon the comparison.

Abstract: Performing a built-in self-test (BIST) on a memory macro includes generating a plurality of input vectors such that at least one input vector of the plurality of input vectors is transmitted to the memory macro in each of a plurality of cycles, receiving in each of the plurality of cycles, an output data from the memory macro. The output data is generated by the memory macro in response to processing the at least one input vector. The BIST also includes comparing the output data in each of the plurality of cycles with a signature value and determining whether the memory macro is normal or faulty based upon the comparison.

Abstract: Systems and methods for floating-point processors and methods for operating floating-point processors are provided. A floating-point processor includes a quantizer, a compute-in-memory device, and a decoder. The floating-processor is configured to receive an input array in which the values of the input array are represented in floating-point format. The floating-point processor may be configured to convert the floating-point numbers into integer format so that multiply-accumulate operations can be performed on the numbers. The multiply-accumulate operations generate partial sums, which are in integer format. The partial sums can be accumulated until a full sum is achieved, wherein the full sum can then be converted to floating-point format.

Abstract: Performing a built-in self-test (BIST) on a memory macro includes generating a plurality of input vectors such that at least one input vector of the plurality of input vectors is transmitted to the memory macro in each of a plurality of cycles, receiving in each of the plurality of cycles, an output data from the memory macro. The output data is generated by the memory macro in response to processing the at least one input vector. The BIST also includes comparing the output data in each of the plurality of cycles with a signature value and determining whether the memory macro is normal or faulty based upon the comparison.

Abstract: Performing a built-in self-test (BIST) on a memory macro includes generating a plurality of input vectors. One input vector is transmitted to the memory macro in each of a plurality of cycles. Each of the plurality of input vectors is associated with a bit width. Generating the input vector includes generating a partial input vector of half the bit width and transmitting the partial input vector to each of a first half of the memory macro and a second half of the memory macro. The method also includes receiving, in each of the plurality of cycles, an output data from the memory macro, such that the output data is generated by the memory macro in response to processing the partial input vector, comparing the output data with a signature value, and determining whether the memory macro is normal or faulty based upon the comparison.

Abstract: Disclosed herein is related to physical unclonable function (PUF) with enhanced security based on one time programmable (OTP) memory device. In one aspect, indirection process, hashing or a combination of them can be employed to hide a key for allowing access to an integrated circuit. Each indirection process may include identifying a subsequent address of the OTP memory device based on content stored by the OTP memory device at an address, and obtaining subsequent content stored by the OTP memory device at the subsequent address. Through a number of indirection processes, hidden content stored by the OTP memory device can be obtained. In one approach, hashing can be applied to input bits to obtain an address of the OTP memory device to apply. In one approach, hashing can be applied to the hidden content stored by the OTP memory device to generate the key.

Abstract: This description relates to a system for storing repair data of a random access memory (RAM) array in a one-time programming memory (OTPM). The system includes the RAM array, wherein the RAM array includes a main memory, redundant rows and columns, and a first repair register memory. The system further includes a built-in self-test-and-repair (BISTR) module having a second repair register memory, wherein the BISTR module is used to test and repair the RAM array. The system further includes the one-time programming memory (OTPM) for storing repair data from more than one test and repair stages for the RAM array, wherein the repair data from different test and repair stages are stored in a same data segment.

Abstract: This description relates to a system for storing repair data of a random access memory (RAM) array in a one-time programming memory (OTPM). The system includes the RAM array, wherein the RAM array includes a main memory, redundant rows and columns, and a first repair register memory. The system further includes a built-in self-test-and-repair (BISTR) module having a second repair register memory, wherein the BISTR module is used to test and repair the RAM array. The system further includes the one-time programming memory (OTPM) for storing repair data from more than one test and repair stages for the RAM array, wherein the repair data from different test and repair stages are stored in a same data segment.

Abstract: A self-testable digital integrator comprises binary adding apparatus and storage apparatus. The adding apparatus and the storage apparatus are functionally interconnected such that the storage apparatus feeds digital words to the adding apparatus for addition thereof and the adding apparatus feeds resulting digital words to the storage apparatus for storage thereof to perform a digital integration operation. The digital integrator further comprises a first combinational network responsive to a first state of a test mode signal to feed an external input signal to the adding apparatus for integration thereof, and responsive to a second state of the test mode signal to feed to the adding apparatus a test pattern signal derived from selected bias of the digital words fed from the adding apparatus to the storage apparatus.