Patents by Inventor Saman Jafarlou
Saman Jafarlou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11947200Abstract: The present disclosure relates to optical phase modulation devices. The optical phase modulation devices may include a heater resistance which induces a phase change and control systems and methods of controlling the induced phase change.Type: GrantFiled: September 30, 2020Date of Patent: April 2, 2024Assignee: MACOM Technology Solutions Holdings, Inc.Inventors: Quazi Ikram, Ronald Scott Karfelt, Steven Nguyen, Nicholas Karfelt, Saman Jafarlou, Swetha Babu
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Patent number: 11658644Abstract: A method and system for controlling duty cycle distortion in a signal. The system includes an input configured to receive a square wave input signal and a filter configured to transform the square wave input signal into a signal with sloped transitions. One or more linear buffers introduce duty cycle distortion into the signal based on a duty cycle distortion signal to create a duty cycle distorted signal. One or more output buffers receive and transform the duty cycle distorted signal into a distorted square wave signal. A feedback loop receives the distorted square wave signal and compares it to a duty cycle distortion control signal to generate an error signal, which indicates the difference between the square wave signal and the desired output duty cycle. The error signal is converted to the duty cycle distortion signal and presented to the one or more linear buffers.Type: GrantFiled: December 6, 2021Date of Patent: May 23, 2023Assignee: MACOM Technology Solutions Holdings, Inc.Inventors: Dario Soltesz, Quazi Ikram, Saman Jafarlou
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Patent number: 11616529Abstract: A cable equalizer configured as part of a cable comprising a first stage, a second stage, and a third stage. The first stage comprises a first stage bias current circuit configured to generate a bias current and a pre-emphasis module configured to introduce pre-emphasis into a received signal to counter the effects of signal amplification. Also part of the first stage is a bias voltage circuit configured to provide a bias voltage to the first stage. The second stage comprises a buffer configured impedance match the first stage. The third stage comprises a third stage bias current circuit configured to generate a bias current and a tank equalizer circuit configured to perform frequency specific equalization on a second stage signal. An amplifier is configured to amplify the second stage signal to create an amplified signal, which is output from the cable equalizer by an output driver.Type: GrantFiled: February 12, 2021Date of Patent: March 28, 2023Assignee: MACOM Technology Solutions Holdings, Inc.Inventors: Quazi Ikram, Naga Rajesh Doppalapudi, Saman Jafarlou
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Publication number: 20220263540Abstract: A cable equalizer configured as part of a cable comprising a first stage, a second stage, and a third stage. The first stage comprises a first stage bias current circuit configured to generate a bias current and a pre-emphasis module configured to introduce pre-emphasis into a received signal to counter the effects of signal amplification. Also part of the first stage is a bias voltage circuit configured to provide a bias voltage to the first stage. The second stage comprises a buffer configured impedance match the first stage. The third stage comprises a third stage bias current circuit configured to generate a bias current and a tank equalizer circuit configured to perform frequency specific equalization on a second stage signal. An amplifier is configured to amplify the second stage signal to create an amplified signal, which is output from the cable equalizer by an output driver.Type: ApplicationFiled: February 12, 2021Publication date: August 18, 2022Inventors: Quazi Ikram, Naga Rajesh Doppalapudi, Saman Jafarlou
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Publication number: 20220182042Abstract: A method and system for controlling duty cycle distortion in a signal. The system includes an input configured to receive a square wave input signal and a filter configured to transform the square wave input signal into a signal with sloped transitions. One or more linear buffers introduce duty cycle distortion into the signal based on a duty cycle distortion signal to create a duty cycle distorted signal. One or more output buffers receive and transform the duty cycle distorted signal into a distorted square wave signal. A feedback loop receives the distorted square wave signal and compares it to a duty cycle distortion control signal to generate an error signal, which indicates the difference between the square wave signal and the desired output duty cycle. The error signal is converted to the duty cycle distortion signal and presented to the one or more linear buffers.Type: ApplicationFiled: December 6, 2021Publication date: June 9, 2022Inventors: Dario Soltesz, Quazi Ikram, Saman Jafarlou
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Publication number: 20210096401Abstract: The present disclosure relates to optical phase modulation devices. The optical phase modulation devices may include a heater resistance which induces a phase change and control systems and methods of controlling the induced phase change.Type: ApplicationFiled: September 30, 2020Publication date: April 1, 2021Inventors: Quazi Ikram, Ronald Scott Karfelt, Steven Nguyen, Nicholas Karfelt, Saman Jafarlou, Swetha Babu
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Patent number: 9577340Abstract: An antenna apparatus includes a waveguide adapter plate for mounting an antenna flange and an RF system-in-package or other IC package. The waveguide adapter plate comprises a first surface and an opposing second surface and a waveguide flange interface. The waveguide flange interface comprises a waveguide channel section extending between the first surface and the second surface and a set of flange mounting holes extending from the first surface to the second surface. The waveguide adapter plate further includes a plurality of substrate alignment pins extending substantially perpendicular from the second surface.Type: GrantFiled: March 18, 2014Date of Patent: February 21, 2017Assignee: PERASO TECHNOLOGIES INC.Inventors: Mohammad Fakharzadeh, Andrew Charles Andrade, Saman Jafarlou, Bradley Robert Lynch, Mihai Tazlauanu
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Patent number: 9515385Abstract: A coplanar waveguide (CPW) apparatus comprises a substrate having a first surface and an opposing second surface. The substrate comprises a metal layer proximate to the first surface. The metal layer comprises a conductive trace comprising a signal line coupled to a launcher element at a first end of the signal line, and a ground plane co-planar with the conductive trace. The ground plane defines a substantially rectangular first region surrounding the launcher element and defining a second region surrounding the signal line, the first and second regions substantially devoid of conductive material. The launcher element has a substantially rectangular shape with a width greater than a width of the signal line at the first end.Type: GrantFiled: March 18, 2014Date of Patent: December 6, 2016Assignee: PERASO TECHNOLOGIES INC.Inventors: Saman Jafarlou, Mohammad Fakharzadeh
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Patent number: 9419341Abstract: An IC package includes an IC die disposed at a first surface of a substrate, which includes a signal via extending between first and second metal layers. The first metal layer is proximate to the first surface and includes a first coplanar waveguide. The first coplanar waveguide has a first signal line coupling a die bump to the signal via and has a first ground plane co-planar with the first signal line. The second metal layer is proximate to a second surface and includes a second coplanar waveguide that has a second signal line coupling the signal via to a launcher element and has a second ground plane co-planar with the second signal line. The IC package further includes a waveguide channel aperture comprising a region surrounding the launcher element and which is substantially devoid of conductive material and a via fence disposed at a perimeter of the first region.Type: GrantFiled: March 18, 2014Date of Patent: August 16, 2016Assignee: Peraso Technologies Inc.Inventors: Saman Jafarlou, Mohammad Fakharzadeh
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Publication number: 20160164189Abstract: A coplanar waveguide (CPW) apparatus comprises a substrate having a first surface and an opposing second surface. The substrate comprises a metal layer proximate to the first surface. The metal layer comprises a conductive trace comprising a signal line coupled to a launcher element at a first end of the signal line, and a ground plane co-planar with the conductive trace. The ground plane defines a substantially rectangular first region surrounding the launcher element and defining a second region surrounding the signal line, the first and second regions substantially devoid of conductive material. The launcher element has a substantially rectangular shape with a width greater than a width of the signal line at the first end.Type: ApplicationFiled: March 18, 2014Publication date: June 9, 2016Applicant: Peraso Technologies, Inc.Inventors: Saman Jafarlou, Mohammad Fakharzadeh
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Publication number: 20150270617Abstract: An antenna apparatus includes a waveguide adapter plate for mounting an antenna flange and an RF system-in-package or other IC package. The waveguide adapter plate comprises a first surface and an opposing second surface and a waveguide flange interface. The waveguide flange interface comprises a waveguide channel section extending between the first surface and the second surface and a set of flange mounting holes extending from the first surface to the second surface. The waveguide adapter plate further includes a plurality of substrate alignment pins extending substantially perpendicular from the second surface.Type: ApplicationFiled: March 18, 2014Publication date: September 24, 2015Applicant: Peraso Technologies, Inc.Inventors: Mohammad Fakharzadeh, Andrew Charles Andrade, Saman Jafarlou, Bradley Robert Lynch, Mihai Tazlauanu
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Publication number: 20150270616Abstract: An IC package includes an IC die disposed at a first surface of a substrate, which includes a signal via extending between first and second metal layers. The first metal layer is proximate to the first surface and includes a first coplanar waveguide. The first coplanar waveguide has a first signal line coupling a die bump to the signal via and has a first ground plane co-planar with the first signal line. The second metal layer is proximate to a second surface and includes a second coplanar waveguide that has a second signal line coupling the signal via to a launcher element and has a second ground plane co-planar with the second signal line. The IC package further includes a waveguide channel aperture comprising a region surrounding the launcher element and which is substantially devoid of conductive material and a via fence disposed at a perimeter of the first region.Type: ApplicationFiled: March 18, 2014Publication date: September 24, 2015Applicant: Peraso Technologies, Inc.Inventors: Saman Jafarlou, Mohammad Fakharzadeh