Abstract: A receiver architecture is disclosed which employs an RC double-sampling front-end and dynamic offset modulation technique. A low-voltage double-sampling technique provides high power efficiency by avoiding linear high-gain elements conventionally employed in typical transimpedance-amplifier (TIA) receivers. In addition, a demultiplexed output of the receiver helps save power in the subsequent digital blocks. Various applications are described including optical receivers, electrical on-chip interconnects, as well as pulse amplitude modulation. The receiver can be implemented in CMOS and is scalable and portable to other technologies.

Abstract: Systems, methods, and devices are provided to reduce or eliminate mura artifacts on electronic displays. For example, pixels may be programmed to a uniform gray level before all or a substantial number of gates of the pixels are activated. The voltages on some or all source lines that supply the pixels may be measured. A mura artifact may be seen when voltage differences on the source lines are present. As such, operational parameters of the electronic display may be adjusted to reduce or eliminate the mura artifact by reducing the voltage differences.

Abstract: The present disclosure is directed to systems and methods for determining sheet resistance values in a liquid crystal display (LCD) panel. In certain embodiments, a system for determining sheet resistance values in an LCD panel may include a display driver integrated circuit (IC). The display driver IC may include a first switch coupled to a first input/output (I/O) pad and a second I/O pad such that the first I/O pad is configured to couple to a voltage source and the second I/O pad is configured to couple to a current source. The display driver IC may also include a second switch coupled to a third I/O pad and the second I/O pad such that the second switch has substantially the same geometry as the first switch and the third I/O pad is configured to couple to a thin-film transistor (TFT) layer of the display panel.

Abstract: The present disclosure is directed to systems and methods for determining sheet resistance values in a liquid crystal display (LCD) panel. In certain embodiments, a system for determining sheet resistance values in an LCD panel may include a display driver integrated circuit (IC). The display driver IC may include a first switch coupled to a first input/output (I/O) pad and a second I/O pad such that the first I/O pad is configured to couple to a voltage source and the second I/O pad is configured to couple to a current source. The display driver IC may also include a second switch coupled to a third I/O pad and the second I/O pa such that the second switch has substantially the same geometry as the first switch and the third I/O pad is configured to couple to a thin-film transistor (TFT) layer of the display panel.

Abstract: A resistor having a known resistance is coupled in series with a device under test (DUT) having an unknown capacitance. An ac signal source having a known fundamental frequency is coupled to drive the resistor to thereby produce a first ac signal. A phase controllable signal generator produces a second ac signal. The first and second ac signals are fed to a mixer. An output of the mixer is low pass filtered. A peak detector monitors the low pass filtered output while sweeping the phase controllable signal generator, until a peak is detected. The set phase corresponding to the detected peak is then used to obtain an estimate of the unknown DUT capacitance. Other embodiments are also described and claimed.

Abstract: Systems, methods, and devices are provided to reduce or eliminate mura artifacts on electronic displays. For example, pixels may be programmed to a uniform gray level before all or a substantial number of gates of the pixels are activated. The voltages on some or all source lines that supply the pixels may be measured. A mura artifact may be seen when voltage differences on the source lines are present. As such, operational parameters of the electronic display may be adjusted to reduce or eliminate the mura artifact by reducing the voltage differences.

Abstract: A receiver architecture is disclosed which employs an RC double-sampling front-end and dynamic offset modulation technique. A low-voltage double-sampling technique provides high power efficiency by avoiding linear high-gain elements conventionally employed in typical transimpedance-amplifier (TIA) receivers. In addition, a demultiplexed output of the receiver helps save power in the subsequent digital blocks. Various applications are described including optical receivers, electrical on-chip interconnects, as well as pulse amplitude modulation. The receiver can be implemented in CMOS and is scalable and portable to other technologies.