Abstract: Silicon-on-insulator JFET (SOI JFET) having a fully depleted body and fabrication methods therefor. SOI JFETs offer leakage advantages over bulk silicon JFETs. However, some SOI JFETs have poor switching characteristics (e.g., high switch on time). The devices and techniques include a fully-depleted body SOI-JFET, with improved switching characteristic over partially-depleted SOI JFET or bulk silicon devices. In one example, by tuning the thickness of the silicon containing layer of the SOI substrate, the body region of the JFET can be fully depleted during the OFF-state thus offering the performance benefits of suppressed leakage current. Additionally, improved AC performance (e.g., faster switching time) is achieved.

Abstract: Junction field-effect transistors (JFETs) having insulator-isolated source/drain regions and fabrication methods therefor are disclosed here. In SOI JFETs and bulk silicon JFETs having junction isolated source and drain regions from the body region, the junction leakage current is one of the leakage components of the off-state leakage current and consequently limits the on-off switching performance. In particular, for short-channel devices (for example, sub-100 nm and/or sub-65 nm devices), the leakage currents are especially pronounced. The techniques herein introduced include JFET with an insulating spacer such that the source and drain regions are insulator isolated from the body region. In one embodiment, the source and drain regions of the transistor are insulator isolated by silicon dioxide thus reducing the source-drain to body junction leakage current and improved on-off performance.

Abstract: Silicon-on-insulator JFET having a body bias and a fully depleted body and fabrication methods therefore are disclosed. SOI JFETs offer leakage advantages over bulk silicon JFETs. However, some SOI JFETs have poor switching characteristics (e.g., high switch on time), and have poor leakage performance at high temperatures. The techniques herein introduced include a fully-depleted body SOI-JFET, with a non-zero bias applied to its body. In one example, the body region of the JFET can be fully depleted by tuning the thickness of the silicon containing layer of the SOI substrate. Additionally, the deep depletion can be induced by applying a non-zero bias to the body region, at a range of operating temperatures. Full body depletion and/or the application of body bias offers the benefits of suppressed leakage current at higher operating temperatures (e.g., between or above 25-115 C) and improved AC performance (e.g., faster switching time).

Abstract: A method for forming a semiconductor device with a doped channel-region, and the device formed therefrom. In one embodiment, the method invention is comprised of two principal steps. The first step is to provide a semiconductor substrate to which the following process steps can be performed. The second step is to create a doping profile into the channel-region of the semiconductor substrate. The doping profile is created by a) performing a first doping implantation with a first dopant in a first concentration to a first depth within the semiconductor substrate, and b) performing a second doping implantation with a second dopant in a second concentration to a second depth within the semiconductor substrate.