Patents by Inventor Samatha J. Edirisooriya

Samatha J. Edirisooriya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Conditional read and invalidate for use in coherent multiprocessor systems
    Publication number: 20030195939
    Abstract: A conditional read and invalidate operation for use in coherent multiprocessor systems is disclosed. A conditional read and invalidate request may be sent via an interconnection network from a first processor that requires exclusive access to a cache block to a second processor that requires exclusive access to the cache block. Data associated with the cache block may be sent from the second processor to the first processor in response to the conditional read and invalidate request and a determination that the cache block is associated with a state of a cache coherency protocol.
    Type: Application
    Filed: April 16, 2002
    Publication date: October 16, 2003
    Inventors: Samatha J. Edirisooriya, Sujat Jamil, David E. Miner, R. Frank O'Bleness, Steven J. Tu, Hang T. Nguyen