Abstract: The invention provides a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device, among others, may include forming one or more layers of material within an opening in a substrate, the opening and the one or more layers forming at least a portion of an isolation structure, and subjecting at least one of the one or more layers to an energy beam treatment, the energy beam treatment configured to change a stress of the one or more layers subjected thereto, and thus change a stress in the substrate.

Abstract: The present invention provides a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device, among other steps, may include forming a gate structure over a substrate, forming at least a portion of gate sidewall spacers proximate sidewalls of the gate structure, and subjecting the at least a portion of the gate sidewall spacers to an energy beam treatment, the energy beam treatment configured to change a stress of the at least a portion of the gate sidewall spacers, and thus change a stress in the substrate therebelow.

Abstract: The invention provides a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device, among others, may include forming one or more layers of material within an opening in a substrate, the opening and the one or more layers forming at least a portion of an isolation structure, and subjecting at least one of the one or more layers to an energy beam treatment, the energy beam treatment configured to change a stress of the one or more layers subjected thereto, and thus change a stress in the substrate.

Abstract: The present invention provides a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device, among other steps, may include forming a gate structure over a substrate, forming at least a portion of gate sidewall spacers proximate sidewalls of the gate structure, and subjecting the at least a portion of the gate sidewall spacers to an energy beam treatment, the energy beam treatment configured to change a stress of the at least a portion of the gate sidewall spacers, and thus change a stress in the substrate therebelow.

Abstract: The present invention provides a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device includes, among other steps, forming a gate structure over a substrate, the gate structure having source/drain regions proximate thereto and in, on or over the substrate, forming a pre-metal dielectric layer over the gate structure and source/drain regions, and subjecting the pre-metal dielectric layer to an energy beam treatment, the energy beam treatment configured to change a stress of the pre-metal dielectric layer, and thus change a stress in the substrate therebelow.

Abstract: A device employs damascene layers with a pore sealing liner and includes a semiconductor body. A metal interconnect layer comprising a metal interconnect is formed over the semiconductor body. A dielectric layer is formed over the metal interconnect layer. A conductive trench feature and a conductive via feature are formed in the dielectric layer. A pore sealing liner is formed only along sidewall of the conductive via feature and along sidewalls and bottom surfaces of the conductive trench feature. The pore sealing liner is not substantially present along a bottom surface of the conductive via feature.

Abstract: MIMCAP semiconductor devices and methods for fabrication MIMCAP semiconductor devices that include a grown capacitor dielectric are provided. Exemplary MIMCAP semiconductor devices can include a bottom electrode, a grown capacitor dielectric on the bottom electrode, and a top electrode on the capacitor dielectric. The grown layer can have a k-value greater than 1 and can be formed of, for example, an oxide or nitride that is chemically or thermally grown from the bottom electrode.

Abstract: A method of forming a semiconductor device including forming a low-k dielectric material over a substrate, depositing a liner on a portion of the low-k dielectric material, and exposing the liner to a plasma. The method also includes depositing a layer over the liner.

Abstract: The formation of a MIM (metal insulator metal) capacitor (164) and concurrent formation of a resistor (166) is disclosed. A copper diffusion barrier (124) is formed over a copper deposition (110) that serves as a bottom electrode (170) of the capacitor (164). The copper diffusion barrier (124) mitigates unwanted diffusion of copper from the copper deposition (110), and is formed via electro-less deposition such that little to none of the barrier material is deposited at locations other than over a top surface (125) of the deposition of copper/bottom electrode. Subsequently, layers of dielectric (150) and conductive (152) materials are applied to form a dielectric (172) and top electrode (174) of the MIM capacitor (164), respectively, where the layer of conductive top electrode material (152) also functions to concurrently develop the resistor (166) on the same chip as the capacitor (164).

Abstract: A trench and via structure is formed in a low k dielectric layer (100) formed over a silicon substrate (10). Super critical CO2 and a first silylization agent are used to form a chemically bonded high density surface layer (160). Silanol species are removed from the low k dielectric layer (100) using super critical CO2 and a second silylization agent. A barrier layer (190) and copper (200) are used to fill the trench and via structure.

Abstract: A method (10) of forming a MIM (metal insulator metal) capacitor is disclosed whereby adverse affects associated with copper diffusion are mitigated even as the capacitor is scaled down. A layer of bottom electrode/copper diffusion barrier material (136) is formed (16) within an aperture (128) wherein the capacitor (100) is to be defined. The bottom electrode layer (136) is formed via a directional process so that a horizontal aspect (138) of the layer (136) is formed over a metal (110) at a bottom of the aperture (128) to a thickness (142) that is greater than a thickness (144) of a sidewall aspect (148) of the layer (136) formed upon sidewalls (132) of the aperture (128). Accordingly, the thinner sidewall aspects (148) are removed during an etching act (18) while some of the thicker horizontal aspect (138) remains. A layer of capacitor dielectric material (150) is then conformally formed (20) into the aperture 128 and over the horizontal aspect (138).

Abstract: A method comprises extracting impurities from one or more materials in a semiconductor device via treatment with a supercritical fluid (SCF). The SCF may comprise a solvent and one or more co-solvents. Solvents may comprise 1-hexanol, 1-propanol, 2-propanol, acetone, ammonia, argon, carbon dioxide, chlorotrifluoromethane, cyclohexane, dichlorodifluoromethane, ethane, ethyl alcohol, ethylene, methane, methanol, n-butane, n-hexane, nitrous oxide, n-pentane, propane, propylene, toluene, trichlorofluoromethane, trichloromethane, water, or combinations thereof.

Abstract: A trench and via structure is formed in a low k dielectric layer (100) formed over a silicon substrate (10). Super critical CO2 and a first silylization agent are used to form a chemically bonded high density surface layer (160). Silanol species are removed from the low k dielectric layer (100) using super critical CO2 and a second silylization agent. A barrier layer (190) and copper (200) are used to fill the trench and via structure.