Patents by Inventor Sameer H. Jain
Sameer H. Jain has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10741554Abstract: A third type of metal gate stack is provided above an isolation structure and between a replacement metal gate n-type field effect transistor and a replacement metal gate p-type field effect transistor. The third type of metal gate stack includes at least three different components. Notably, the third type of metal gate stack includes, as a first component, an n-type workfunction metal layer, as a second component, a p-type workfunction metal layer, and as a third component, a low resistance metal layer. In some embodiments, the uppermost surface of the first, second and third components of the third type of metal gate stack are all substantially coplanar with each other. In other embodiments, an uppermost surface of the third component of the third type of metal gate stack is non-substantially coplanar with an uppermost surface of both the first and second components of the third type of metal gate stack.Type: GrantFiled: March 5, 2019Date of Patent: August 11, 2020Assignee: International Business Machines CorporationInventors: Ramachandra Divakaruni, Sameer H. Jain, Viraj Y. Sardesai, Keith H. Tabakman
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Publication number: 20190206866Abstract: A third type of metal gate stack is provided above an isolation structure and between a replacement metal gate n-type field effect transistor and a replacement metal gate p-type field effect transistor. The third type of metal gate stack includes at least three different components. Notably, the third type of metal gate stack includes, as a first component, an n-type workfunction metal layer, as a second component, a p-type workfunction metal layer, and as a third component, a low resistance metal layer. In some embodiments, the uppermost surface of the first, second and third components of the third type of metal gate stack are all substantially coplanar with each other. In other embodiments, an uppermost surface of the third component of the third type of metal gate stack is non-substantially coplanar with an uppermost surface of both the first and second components of the third type of metal gate stack.Type: ApplicationFiled: March 5, 2019Publication date: July 4, 2019Applicant: International Business Machines CorporationInventors: Ramachandra Divakaruni, Sameer H. Jain, Viraj Y. Sardesai, Keith H. Tabakman
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Patent number: 10262996Abstract: A third type of metal gate stack is provided above an isolation structure and between a replacement metal gate n-type field effect transistor and a replacement metal gate p-type field effect transistor. The third type of metal gate stack includes at least three different components. Notably, the third type of metal gate stack includes, as a first component, an n-type workfunction metal layer, as a second component, a p-type workfunction metal layer, and as a third component, a low resistance metal layer. In some embodiments, the uppermost surface of the first, second and third components of the third type of metal gate stack are all substantially coplanar with each other. In other embodiments, an uppermost surface of the third component of the third type of metal gate stack is non-substantially coplanar with an uppermost surface of both the first and second components of the third type of metal gate stack.Type: GrantFiled: April 24, 2017Date of Patent: April 16, 2019Assignee: International Business Machines CorporationInventors: Ramachandra Divakaruni, Sameer H. Jain, Viraj Y. Sardesai, Keith H. Tabakman
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Publication number: 20170229458Abstract: A third type of metal gate stack is provided above an isolation structure and between a replacement metal gate n-type field effect transistor and a replacement metal gate p-type field effect transistor. The third type of metal gate stack includes at least three different components. Notably, the third type of metal gate stack includes, as a first component, an n-type workfunction metal layer, as a second component, a p-type workfunction metal layer, and as a third component, a low resistance metal layer. In some embodiments, the uppermost surface of the first, second and third components of the third type of metal gate stack are all substantially coplanar with each other. In other embodiments, an uppermost surface of the third component of the third type of metal gate stack is non-substantially coplanar with an uppermost surface of both the first and second components of the third type of metal gate stack.Type: ApplicationFiled: April 24, 2017Publication date: August 10, 2017Applicant: International Business Machines CorporationInventors: Ramachandra Divakaruni, Sameer H. Jain, Viraj Y. Sardesai, Keith H. Tabakman
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Patent number: 9679993Abstract: After formation of gate structures over semiconductor fins and prior to formation of raised active regions, a directional ion beam is employed to form a dielectric material portion on end walls of semiconductor fins that are perpendicular to the lengthwise direction of the semiconductor fins. The angle of the directional ion beam is selected to be with a vertical plane including the lengthwise direction of the semiconductor fins, thereby avoiding formation of the dielectric material portion on lengthwise sidewalls of the semiconductor fins. Selective epitaxy of semiconductor material is performed to grow raised active regions from sidewall surfaces of the semiconductor fins. Optionally, horizontal portions of the dielectric material portion may be removed prior to the selective epitaxy process. Further, the dielectric material portion may optionally be removed after the selective epitaxy process.Type: GrantFiled: June 10, 2016Date of Patent: June 13, 2017Assignee: International Business Machines CorporationInventors: Emre Alptekin, Sameer H. Jain, Viraj Y. Sardesai, Cung D. Tran, Reinaldo A. Vega
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Patent number: 9634006Abstract: A third type of metal gate stack is provided above an isolation structure and between a replacement metal gate n-type field effect transistor and a replacement metal gate p-type field effect transistor. The third type of metal gate stack includes at least three different components. Notably, the third type of metal gate stack includes, as a first component, an n-type workfunction metal layer, as a second component, a p-type workfunction metal layer, and as a third component, a low resistance metal layer. In some embodiments, the uppermost surface of the first, second and third components of the third type of metal gate stack are all substantially coplanar with each other. In other embodiments, an uppermost surface of the third component of the third type of metal gate stack is non-substantially coplanar with an uppermost surface of both the first and second components of the third type of metal gate stack.Type: GrantFiled: February 28, 2014Date of Patent: April 25, 2017Assignee: International Business Machines CorporationInventors: Ramachandra Divakaruni, Sameer H. Jain, Viraj Y. Sardesai, Keith H. Tabakman
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Patent number: 9601380Abstract: After formation of gate structures over semiconductor fins and prior to formation of raised active regions, a directional ion beam is employed to form a dielectric material portion on end walls of semiconductor fins that are perpendicular to the lengthwise direction of the semiconductor fins. The angle of the directional ion beam is selected to be with a vertical plane including the lengthwise direction of the semiconductor fins, thereby avoiding formation of the dielectric material portion on lengthwise sidewalls of the semiconductor fins. Selective epitaxy of semiconductor material is performed to grow raised active regions from sidewall surfaces of the semiconductor fins. Optionally, horizontal portions of the dielectric material portion may be removed prior to the selective epitaxy process. Further, the dielectric material portion may optionally be removed after the selective epitaxy process.Type: GrantFiled: October 15, 2015Date of Patent: March 21, 2017Assignee: International Business Machines CorporationInventors: Emre Alptekin, Sameer H. Jain, Viraj Y. Sardesai, Cung D. Tran, Reinaldo A. Vega
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Patent number: 9515168Abstract: After formation of gate structures over semiconductor fins and prior to formation of raised active regions, a directional ion beam is employed to form a dielectric material portion on end walls of semiconductor fins that are perpendicular to the lengthwise direction of the semiconductor fins. The angle of the directional ion beam is selected to be with a vertical plane including the lengthwise direction of the semiconductor fins, thereby avoiding formation of the dielectric material portion on lengthwise sidewalls of the semiconductor fins. Selective epitaxy of semiconductor material is performed to grow raised active regions from sidewall surfaces of the semiconductor fins. Optionally, horizontal portions of the dielectric material portion may be removed prior to the selective epitaxy process. Further, the dielectric material portion may optionally be removed after the selective epitaxy process.Type: GrantFiled: October 15, 2015Date of Patent: December 6, 2016Assignee: International Business Machines CorporationInventors: Emre Alptekin, Sameer H. Jain, Viraj Y. Sardesai, Cung D. Tran, Reinaldo A. Vega
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Patent number: 9514992Abstract: A semiconductor device includes a trench region in an interconnect level dielectric layer. A silicide layer is on the bottom of the trench region. Opposing minor sides of the trench region include a spacer layer, but the central portion of the trench region is substantially free from the spacer layer. The spacer layer is formed using an angled gas cluster ion beam.Type: GrantFiled: May 7, 2015Date of Patent: December 6, 2016Assignee: International Business Machines CorporationInventors: Emre Alptekin, Sameer H. Jain, Unoh Kwon, Zhengwen Li, Hari V. Mallela, Ayse M. Ozbek, Cung D. Tran, Reinaldo A. Vega, Richard S. Wise
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Publication number: 20160329251Abstract: A semiconductor device includes a trench region in an interconnect level dielectric layer. A silicide layer is on the bottom of the trench region. Opposing minor sides of the trench region include a spacer layer, but the central portion of the trench region is substantially free from the spacer layer. The spacer layer is formed using an angled gas cluster ion beam.Type: ApplicationFiled: May 7, 2015Publication date: November 10, 2016Inventors: Emre Alptekin, Sameer H. Jain, Unoh Kwon, Zhengwen Li, Hari V. Mallela, Ayse M. Ozbek, Cung D. Tran, Reinaldo A. Vega, Richard S. Wise
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Publication number: 20160284598Abstract: After formation of gate structures over semiconductor fins and prior to formation of raised active regions, a directional ion beam is employed to form a dielectric material portion on end walls of semiconductor fins that are perpendicular to the lengthwise direction of the semiconductor fins. The angle of the directional ion beam is selected to be with a vertical plane including the lengthwise direction of the semiconductor fins, thereby avoiding formation of the dielectric material portion on lengthwise sidewalls of the semiconductor fins. Selective epitaxy of semiconductor material is performed to grow raised active regions from sidewall surfaces of the semiconductor fins. Optionally, horizontal portions of the dielectric material portion may be removed prior to the selective epitaxy process. Further, the dielectric material portion may optionally be removed after the selective epitaxy process.Type: ApplicationFiled: June 10, 2016Publication date: September 29, 2016Inventors: Emre Alptekin, Sameer H. Jain, Viraj Y. Sardesai, Cung D. Tran, Reinaldo A. Vega
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Patent number: 9391175Abstract: After formation of gate structures over semiconductor fins and prior to formation of raised active regions, a directional ion beam is employed to form a dielectric material portion on end walls of semiconductor fins that are perpendicular to the lengthwise direction of the semiconductor fins. The angle of the directional ion beam is selected to be with a vertical plane including the lengthwise direction of the semiconductor fins, thereby avoiding formation of the dielectric material portion on lengthwise sidewalls of the semiconductor fins. Selective epitaxy of semiconductor material is performed to grow raised active regions from sidewall surfaces of the semiconductor fins. Optionally, horizontal portions of the dielectric material portion may be removed prior to the selective epitaxy process. Further, the dielectric material portion may optionally be removed after the selective epitaxy process.Type: GrantFiled: October 15, 2015Date of Patent: July 12, 2016Assignee: International Business Machines CorporationInventors: Emre Alptekin, Sameer H. Jain, Viraj Y. Sardesai, Cung D. Tran, Reinaldo A. Vega
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Patent number: 9349836Abstract: After formation of gate structures over semiconductor fins and prior to formation of raised active regions, a directional ion beam is employed to form a dielectric material portion on end walls of semiconductor fins that are perpendicular to the lengthwise direction of the semiconductor fins. The angle of the directional ion beam is selected to be with a vertical plane including the lengthwise direction of the semiconductor fins, thereby avoiding formation of the dielectric material portion on lengthwise sidewalls of the semiconductor fins. Selective epitaxy of semiconductor material is performed to grow raised active regions from sidewall surfaces of the semiconductor fins. Optionally, horizontal portions of the dielectric material portion may be removed prior to the selective epitaxy process. Further, the dielectric material portion may optionally be removed after the selective epitaxy process.Type: GrantFiled: January 14, 2014Date of Patent: May 24, 2016Assignee: International Business Machines CorporationInventors: Emre Alptekin, Sameer H. Jain, Viraj Y. Sardesai, Cung D. Tran, Reinaldo A. Vega
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Patent number: 9331166Abstract: Angled directional ion beams are directed to sidewalls of a gate structure that straddles at least one semiconductor fin. The directions of the angled directional ion beams are contained within a vertical plane that is parallel to the sidewalls of the at least one semiconductor. A pair of gate spacers are formed on sidewalls of the gate structure by accumulation of the deposited dielectric material from the angled directional ion beams and without use of an anisotropic etch, while the sidewalls of the semiconductor fins parallel to the directional ion beams remain physically exposed. A selective epitaxy process can be performed to form raised active regions by growing a semiconductor material from the sidewalls of the semiconductor fins.Type: GrantFiled: October 21, 2014Date of Patent: May 3, 2016Assignee: International Business Machines CorporationInventors: Emre Alptekin, Sameer H. Jain, Viraj Y. Sardesai, Cung D. Tran, Reinaldo A. Vega
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Publication number: 20160035875Abstract: After formation of gate structures over semiconductor fins and prior to formation of raised active regions, a directional ion beam is employed to form a dielectric material portion on end walls of semiconductor fins that are perpendicular to the lengthwise direction of the semiconductor fins. The angle of the directional ion beam is selected to be with a vertical plane including the lengthwise direction of the semiconductor fins, thereby avoiding formation of the dielectric material portion on lengthwise sidewalls of the semiconductor fins. Selective epitaxy of semiconductor material is performed to grow raised active regions from sidewall surfaces of the semiconductor fins. Optionally, horizontal portions of the dielectric material portion may be removed prior to the selective epitaxy process. Further, the dielectric material portion may optionally be removed after the selective epitaxy process.Type: ApplicationFiled: October 15, 2015Publication date: February 4, 2016Inventors: Emre Alptekin, Sameer H. Jain, Viraj Y. Sardesai, Cung D. Tran, Reinaldo A. Vega
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Publication number: 20160035876Abstract: After formation of gate structures over semiconductor fins and prior to formation of raised active regions, a directional ion beam is employed to form a dielectric material portion on end walls of semiconductor fins that are perpendicular to the lengthwise direction of the semiconductor fins. The angle of the directional ion beam is selected to be with a vertical plane including the lengthwise direction of the semiconductor fins, thereby avoiding formation of the dielectric material portion on lengthwise sidewalls of the semiconductor fins. Selective epitaxy of semiconductor material is performed to grow raised active regions from sidewall surfaces of the semiconductor fins. Optionally, horizontal portions of the dielectric material portion may be removed prior to the selective epitaxy process. Further, the dielectric material portion may optionally be removed after the selective epitaxy process.Type: ApplicationFiled: October 15, 2015Publication date: February 4, 2016Inventors: Emre Alptekin, Sameer H. Jain, Viraj Y. Sardesai, Cung D. Tran, Reinaldo A. Vega
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Publication number: 20160035864Abstract: After formation of gate structures over semiconductor fins and prior to formation of raised active regions, a directional ion beam is employed to form a dielectric material portion on end walls of semiconductor fins that are perpendicular to the lengthwise direction of the semiconductor fins. The angle of the directional ion beam is selected to be with a vertical plane including the lengthwise direction of the semiconductor fins, thereby avoiding formation of the dielectric material portion on lengthwise sidewalls of the semiconductor fins. Selective epitaxy of semiconductor material is performed to grow raised active regions from sidewall surfaces of the semiconductor fins. Optionally, horizontal portions of the dielectric material portion may be removed prior to the selective epitaxy process. Further, the dielectric material portion may optionally be removed after the selective epitaxy process.Type: ApplicationFiled: October 15, 2015Publication date: February 4, 2016Inventors: Emre Alptekin, Sameer H. Jain, Viraj Y. Sardesai, Cung D. Tran, Reinaldo A. Vega
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Publication number: 20150270365Abstract: Angled directional ion beams are directed to sidewalls of a gate structure that straddles at least one semiconductor fin. The directions of the angled directional ion beams are contained within a vertical plane that is parallel to the sidewalls of the at least one semiconductor. A pair of gate spacers are formed on sidewalls of the gate structure by accumulation of the deposited dielectric material from the angled directional ion beams and without use of an anisotropic etch, while the sidewalls of the semiconductor fins parallel to the directional ion beams remain physically exposed. A selective epitaxy process can be performed to form raised active regions by growing a semiconductor material from the sidewalls of the semiconductor fins.Type: ApplicationFiled: October 21, 2014Publication date: September 24, 2015Inventors: Emre Alptekin, Sameer H. Jain, Viraj Y. Sardesai, Cung D. Tran, Reinaldo A. Vega
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Publication number: 20150249086Abstract: A third type of metal gate stack is provided above an isolation structure and between a replacement metal gate n-type field effect transistor and a replacement metal gate p-type field effect transistor. The third type of metal gate stack includes at least three different components. Notably, the third type of metal gate stack includes, as a first component, an n-type workfunction metal layer, as a second component, a p-type workfunction metal layer, and as a third component, a low resistance metal layer. In some embodiments, the uppermost surface of the first, second and third components of the third type of metal gate stack are all substantially coplanar with each other. In other embodiments, an uppermost surface of the third component of the third type of metal gate stack is non-substantially coplanar with an uppermost surface of both the first and second components of the third type of metal gate stack.Type: ApplicationFiled: February 28, 2014Publication date: September 3, 2015Applicant: International Business Machines CorporationInventors: Ramachandra Divakaruni, Sameer H. Jain, Viraj Y. Sardesai, Keith H. Tabakman
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Patent number: 9111962Abstract: Angled directional ion beams are directed to sidewalls of a gate structure that straddles at least one semiconductor fin. The directions of the angled directional ion beams are contained within a vertical plane that is parallel to the sidewalls of the at least one semiconductor. A pair of gate spacers are formed on sidewalls of the gate structure by accumulation of the deposited dielectric material from the angled directional ion beams and without use of an anisotropic etch, while the sidewalls of the semiconductor fins parallel to the directional ion beams remain physically exposed. A selective epitaxy process can be performed to form raised active regions by growing a semiconductor material from the sidewalls of the semiconductor fins.Type: GrantFiled: March 20, 2014Date of Patent: August 18, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Emre Alptekin, Sameer H. Jain, Viraj Y. Sardesai, Cung D. Tran, Reinaldo A. Vega