Patents by Inventor Sameer PAITAL
Sameer PAITAL has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240178145Abstract: Embodiments include an electronic package with an embedded multi-interconnect bridge (EMIB) and methods of making such packages. Embodiments include a first layer, that is an organic material and a second layer disposed over the first layer. In an embodiment, a cavity is formed through the second layer to expose a first surface of the first layer. A bridge substrate is in the cavity and is supported by the first surface of the first layer. Embodiments include a first die over the second layer that is electrically coupled to a first contact on the bridge substrate, and a second die over the second layer that is electrically coupled to a second contact on the bridge substrate. In an embodiment the first die is electrically coupled to the second die by the bridge substrate.Type: ApplicationFiled: February 6, 2024Publication date: May 30, 2024Inventors: Kristof DARMAWIKARTA, Hiroki TANAKA, Robert MAY, Sameer PAITAL, Bai NIE, Jesse JONES, Chung Kwang Christopher TAN
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Publication number: 20240114623Abstract: An electronic device includes a substrate including a glass core layer and first contact pads on a first surface of the glass core layer; one or more discrete passive electronic components disposed on the first surface of the glass core layer, the one or more discrete passive electronic components including second contact pads on a bottom surface of the one or more discrete passive electronic components; and hybrid bonds between the first contact pads of the glass core layer and the second contact pads of the one or more discrete passive electronic components.Type: ApplicationFiled: September 29, 2022Publication date: April 4, 2024Inventors: Kristof Darmawikarta, Srinivas Venkata Ramanuja Pietambaram, Gang Duan, Sameer Paital
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Publication number: 20240088052Abstract: A die assembly is disclosed. The die assembly includes a die, one or more die pads on a first surface of the die and a die attach film on the die where the die attach film includes one or more openings that expose the one or more die pads and that extend to one or more edges of the die.Type: ApplicationFiled: November 17, 2023Publication date: March 14, 2024Inventors: Bai NIE, Gang DUAN, Srinivas PIETAMBARAM, Jesse JONES, Yosuke KANAOKA, Hongxia FENG, Dingying XU, Rahul MANEPALLI, Sameer PAITAL, Kristof DARMAWIKARTA, Yonggang LI, Meizi JIAO, Chong ZHANG, Matthew TINGEY, Jung Kyu HAN, Haobo CHEN
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Patent number: 11929212Abstract: Embodiments disclosed herein include an electronic package and methods of forming an electronic package. In an embodiment, the electronic package comprises a package substrate, an organic layer over the package substrate, and a capacitor embedded in the organic layer. In an embodiment, the capacitor comprises, a first electrode, where the first electrode comprises a seam between a first conductive layer and a second conductive layer, a dielectric layer over the first electrode, and a second electrode over the dielectric layer.Type: GrantFiled: April 23, 2019Date of Patent: March 12, 2024Assignee: Intel CorporationInventors: Sameer Paital, Gang Duan, Srinivas Pietambaram, Kristof Darmawikarta
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Patent number: 11929330Abstract: Embodiments include an electronic package with an embedded multi-interconnect bridge (EMIB) and methods of making such packages. Embodiments include a first layer, that is an organic material and a second layer disposed over the first layer. In an embodiment, a cavity is formed through the second layer to expose a first surface of the first layer. A bridge substrate is in the cavity and is supported by the first surface of the first layer. Embodiments include a first die over the second layer that is electrically coupled to a first contact on the bridge substrate, and a second die over the second layer that is electrically coupled to a second contact on the bridge substrate. In an embodiment the first die is electrically coupled to the second die by the bridge substrate.Type: GrantFiled: April 4, 2022Date of Patent: March 12, 2024Assignee: Intel CorporationInventors: Kristof Darmawikarta, Hiroki Tanaka, Robert May, Sameer Paital, Bai Nie, Jesse Jones, Chung Kwang Christopher Tan
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Patent number: 11923312Abstract: A die assembly is disclosed. The die assembly includes a die, one or more die pads on a first surface of the die and a die attach film on the die where the die attach film includes one or more openings that expose the one or more die pads and that extend to one or more edges of the die.Type: GrantFiled: March 27, 2019Date of Patent: March 5, 2024Assignee: Intel CorporationInventors: Bai Nie, Gang Duan, Srinivas Pietambaram, Jesse Jones, Yosuke Kanaoka, Hongxia Feng, Dingying Xu, Rahul Manepalli, Sameer Paital, Kristof Darmawikarta, Yonggang Li, Meizi Jiao, Chong Zhang, Matthew Tingey, Jung Kyu Han, Haobo Chen
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Publication number: 20230420378Abstract: Embodiments of a microelectronic assembly comprise an interposer comprising a dielectric material and a pad of conductive material having at least one of a ceramic liner and fin structures; at least two integrated circuit (IC) dies coupled to the interposer; and a bridge die in the interposer conductively coupled to the at least two IC dies. The bridge die has a first face and an opposing second face, the first face of the bridge die is proximate to the at least two IC dies, and the second face of the bridge die is in contact with the pad.Type: ApplicationFiled: June 23, 2022Publication date: December 28, 2023Applicant: Intel CorporationInventors: Sameer Paital, Gang Duan, Srinivas V. Pietambaram, Kristof Kuwawi Darmawikarta, Tchefor Ndukum, Vejayakumaran Padavettan, Pooja Wadhwa, Brandon C. Marin
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Publication number: 20230420357Abstract: Embodiments herein relate to systems, apparatuses, or processes directed to forming an LGA pad on a side of a substrate, with a layer of silicon nitride between the LGA pad and a dielectric layer of the substrate. The LGA pad may have a reduced footprint, or a reduced lateral dimension with respect to a plane of the substrate, as compared to legacy LGA pads to reduce insertion loss by reducing the resulting capacitance between the reduced LGA footprint and metal routings within the substrate. The layer of silicon nitride may provide additional mechanical support for the reduced footprint. Other embodiments may be described and/or claimed.Type: ApplicationFiled: June 24, 2022Publication date: December 28, 2023Inventors: Brandon C. MARIN, Suddhasattwa NAD, Srinivas V. PIETAMBARAM, Gang DUAN, Jeremy D. ECTON, Kristof DARMAWIKARTA, Sameer PAITAL
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Patent number: 11728265Abstract: Embodiments include package substrates and a method of forming the package substrates. A package substrate includes a dielectric having a cavity that has a footprint, a resistor embedded in the cavity of the dielectric, and a plurality of traces on the resistor, where a plurality of surfaces of the resistor are activated surfaces. The resistor may also have a plurality of sidewalls which may be activated sidewalls and tapered. The dielectric may include metallization particles/ions. The resistor may include resistive materials, such as nickel-phosphorus (NiP), aluminum-nitride (AlN), and/or titanium-nitride (TiN). The package substrate may further include a first resistor embedded adjacently to the resistor. The first resistor may have a first footprint of a first cavity that is different than the footprint of the cavity of the resistor. The resistor may have a resistance value that is thus different than a first resistance value of the first resistor.Type: GrantFiled: September 12, 2018Date of Patent: August 15, 2023Assignee: Intel CorporationInventors: Brandon C. Marin, Frank Truong, Shivasubramanian Balasubramanian, Dilan Seneviratne, Yonggang Li, Sameer Paital, Darko Grujicic, Rengarajan Shanmugam, Melissa Wette, Srinivas Pietambaram
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Publication number: 20230146165Abstract: Described are microelectronic devices including an embedded microelectronic package for use as an integrated voltage regulator with a microelectronic system. The microelectronic package can include a substrate and a magnetic foil. The substrate can define at least one layer having one or more of electrically conductive elements separated by a dielectric material. The magnetic foil can have ferromagnetic alloy ribbons and can be embedded within the substrate adjacent to the one or more of electrically conductive elements. The magnetic foil can be positioned to interface with and be spaced from the one or more of electrically conductive element.Type: ApplicationFiled: December 30, 2022Publication date: May 11, 2023Inventors: Srinivas PIETAMBARAM, Kristof DARMAWIKARTA, Gang DUAN, Yonggang LI, Sameer PAITAL
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Publication number: 20230087838Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques directed to a protective coating for an edge of a glass layer, in particular a glass core within a substrate of a package, where the protective coating serves to protect the edge of the glass core and fill in cracks at the edges of the glass. This protective coating will decrease cracking during stresses applied to the glass layer during manufacturing or operation. Other embodiments may be described and/or claimed.Type: ApplicationFiled: September 20, 2021Publication date: March 23, 2023Inventors: Rahul N. MANEPALLI, Srinivas V. PIETAMBARAM, Ravindra TANIKELLA, Sameer PAITAL, Gang DUAN
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Publication number: 20230092903Abstract: Methods and apparatus to embed host dies in a substrate are disclosed An apparatus includes a first die having a first side and a second side opposite the first side. The first side includes a first contact to be electrically coupled with a second die. The second side includes a second contact. The apparatus further includes a substrate including a metal layer and a dielectric material on the metal layer. The first die is encapsulated within the dielectric material. The second contact of the first die is bonded to the metal layer independent of an adhesive.Type: ApplicationFiled: September 21, 2021Publication date: March 23, 2023Inventors: Sameer Paital, Gang Duan, Srinivas Pietambaram, Yosuke Kanaoka, Tchefor Ndukum
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Publication number: 20230088392Abstract: Embodiments disclosed herein include electronic packages and methods of assembling such electronic packages. In an embodiment, an electronic package comprises a core, where the core comprises glass. In an embodiment, a first via is through the core, where the first via directly contacts the core. In an embodiment, a second via is through the core, and a sleeve is around the second via. In an embodiment, the sleeve comprises a material with a thermal conductivity that is greater than a thermal conductivity of the second via.Type: ApplicationFiled: September 21, 2021Publication date: March 23, 2023Inventors: Srinivas V. PIETAMBARAM, Gang DUAN, Rahul N. MANEPALLI, Ravindra TANIKELLA, Sameer PAITAL
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Publication number: 20230092242Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques directed to a glass core within a substrate in a package, with one or more through glass vias (TGV) that are filled with a conductive material to electrically couple a first side of the glass core with a second side of the glass layer opposite the first side. A pad, also of conductive material, is electrically and physically coupled with a first and/or second end of the conductive material of the TGV. A layer of dielectric material is between at least a portion of the pad and the surface of the glass core between the pad and the glass core during manufacturing, handling, and/or operation to facilitate a reduction of stress cracks in the glass core. Other embodiments may be described and/or claimed.Type: ApplicationFiled: September 17, 2021Publication date: March 23, 2023Inventors: Srinivas V. PIETAMBARAM, Sameer PAITAL, Kristof DARMAWIKARTA, Hiroki TANAKA, Brandon C. MARIN, Jeremy D. ECTON, Gang DUAN
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Publication number: 20230085411Abstract: A microelectronic assembly is disclosed, comprising: a substrate having a core made of glass; and a first integrated circuit (IC) die and a second IC die coupled to a first side of the substrate. The core comprises a cavity, a third IC die is located within the cavity, and the core further comprises one or more conductive through-glass via (TGV) that facilitates electrical coupling between the first side of the substrate and an opposing second side of the substrate. In some embodiments, the cavity is a blind cavity; in other embodiments, the cavity is a through-hole. In some embodiments, the third IC die merely provides lateral coupling between the first IC die and the second IC die; in other embodiments, the third IC die also provides electrical coupling between the first side and the second side of the substrate with through-silicon vias.Type: ApplicationFiled: September 16, 2021Publication date: March 16, 2023Applicant: Intel CorporationInventors: Sameer Paital, Yonggang Li, Kristof Kuwawi Darmawikarta, Gang Duan, Srinivas V. Pietambaram
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Patent number: 11443885Abstract: Embodiments include inductors and methods of forming inductors. In an embodiment, an inductor may include a substrate core and a conductive through-hole through the substrate core. Embodiments may also include a magnetic sheath around the conductive through hole. In an embodiment, the magnetic sheath is separated from the plated through hole by a barrier layer. In an embodiment, the barrier layer is formed over an inner surface of the magnetic sheath and over first and second surfaces of the magnetic sheath.Type: GrantFiled: March 12, 2018Date of Patent: September 13, 2022Assignee: Intel CorporationInventors: Kristof Darmawikarta, Srinivas Pietambaram, Sandeep Gaan, Sri Ranga Sai Boyapati, Prithwish Chatterjee, Sameer Paital, Rahul Jain, Junnan Zhao
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Publication number: 20220254559Abstract: Described are microelectronic devices including an embedded microelectronic package for use as an integrated voltage regulator with a microelectronic system. The microelectronic package can include a substrate and a magnetic foil. The substrate can define at least one layer having one or more of electrically conductive elements separated by a dielectric material. The magnetic foil can have ferromagnetic alloy ribbons and can be embedded within the substrate adjacent to the one or more of electrically conductive elements. The magnetic foil can be positioned to interface with and be spaced from the one or more of electrically conductive element.Type: ApplicationFiled: April 28, 2022Publication date: August 11, 2022Inventors: Srinivas Venkata Ramanuja Pietambaram, Kristof Darmawikarta, Gang Duan, Yonggang Li, Sameer Paital
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Publication number: 20220223527Abstract: Embodiments include an electronic package with an embedded multi-interconnect bridge (EMIB) and methods of making such packages. Embodiments include a first layer, that is an organic material and a second layer disposed over the first layer. In an embodiment, a cavity is formed through the second layer to expose a first surface of the first layer. A bridge substrate is in the cavity and is supported by the first surface of the first layer. Embodiments include a first die over the second layer that is electrically coupled to a first contact on the bridge substrate, and a second die over the second layer that is electrically coupled to a second contact on the bridge substrate. In an embodiment the first die is electrically coupled to the second die by the bridge substrate.Type: ApplicationFiled: April 4, 2022Publication date: July 14, 2022Inventors: Kristof DARMAWIKARTA, Hiroki TANAKA, Robert MAY, Sameer PAITAL, Bai NIE, Jesse JONES, Chung Kwang Christopher TAN
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Patent number: 11348718Abstract: Described are microelectronic devices including an embedded microelectronic package for use as an integrated voltage regulator with a microelectronic system. The microelectronic package can include a substrate and a magnetic foil. The substrate can define at least one layer having one or more of electrically conductive elements separated by a dielectric material. The magnetic foil can have ferromagnetic alloy ribbons and can be embedded within the substrate adjacent to the one or more of electrically conductive elements. The magnetic foil can be positioned to interface with and be spaced from the one or more of electrically conductive element.Type: GrantFiled: June 29, 2018Date of Patent: May 31, 2022Assignee: Intel CorporationInventors: Srinivas Pietambaram, Kristof Darmawikarta, Gang Duan, Yonggang Li, Sameer Paital
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Publication number: 20220155539Abstract: Embodiments disclosed herein include optical packages. In an embodiment, an optical package comprises a package substrate, and a photonics die coupled to the package substrate. In an embodiment, a compute die is coupled to the package substrate, where the photonics die is communicatively coupled to the compute die by a bridge in the package substrate. In an embodiment, the optical package further comprises an optical waveguide embedded in the package substrate. In an embodiment, a first end of the optical waveguide is below the photonics die, and a second end of the optical waveguide is substantially coplanar with an edge of the package substrate.Type: ApplicationFiled: November 19, 2020Publication date: May 19, 2022Inventors: Srinivas V. PIETAMBARAM, Brandon C. MARIN, Sameer PAITAL, Sai VADLAMANI, Rahul N. MANEPALLI, Xiaoqian LI, Suresh V. POTHUKUCHI, Sujit SHARAN, Arnab SARKAR, Omkar KARHADE, Nitin DESHPANDE, Divya PRATAP, Jeremy ECTON, Debendra MALLIK, Ravindranath V. MAHAJAN, Zhichao ZHANG, Kemal AYGÜN, Bai NIE, Kristof DARMAWIKARTA, James E. JAUSSI, Jason M. GAMBA, Bryan K. CASPER, Gang DUAN, Rajesh INTI, Mozhgan MANSURI, Susheel JADHAV, Kenneth BROWN, Ankar AGRAWAL, Priyanka DOBRIYAL