Patents by Inventor Sameer Sadashiv PAWANEKAR

Sameer Sadashiv PAWANEKAR has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230351564
    Abstract: The present subject matter refers a method of image processing through an artificial neural network implemented in an adapter card in a host-computing system.
    Type: Application
    Filed: April 13, 2021
    Publication date: November 2, 2023
    Inventor: Sameer Sadashiv PAWANEKAR
  • Patent number: 11770345
    Abstract: The present disclosure generally relates to data transfer device for receiving data from a host device and method therefor. The device comprise a plurality of input ports configured to receive input data comprising of a plurality of bytes, an output port configured to provide an output data byte and a plurality of buffer units, each buffer unit coupled to an input port of the plurality of input ports. Each of the plurality of buffer units receives a portion of the input data, wherein an enable bit is associated with the portion of data and each of the buffer devices provides the received portion of data as an output, if the enable bit indicates that the portion of data is not a garbage data.
    Type: Grant
    Filed: November 22, 2021
    Date of Patent: September 26, 2023
    Assignee: US TECHNOLOGY INTERNATIONAL PVT. LTD.
    Inventors: Sameer Sadashiv Pawanekar, Upendra Narayan Tripathi
  • Publication number: 20230098946
    Abstract: The present disclosure generally relates to data transfer device for receiving data from a host device and method therefor. The device comprise a plurality of input ports configured to receive input data comprising of a plurality of bytes, an output port configured to provide an output data byte and a plurality of buffer units, each buffer unit coupled to an input port of the plurality of input ports. Each of the plurality of buffer units receives a portion of the input data, wherein an enable bit is associated with the portion of data and each of the buffer devices provides the received portion of data as an output, if the enable bit indicates that the portion of data is not a garbage data.
    Type: Application
    Filed: November 22, 2021
    Publication date: March 30, 2023
    Inventors: Sameer Sadashiv PAWANEKAR, Upendra Narayan TRIPATHI
  • Publication number: 20230087326
    Abstract: A method of reinforcement learning in a processing element, the method including receiving, by a receiving module, one reward. Further, a computing module computes a Q-value for a first dimension at time tn, based on the reward. The Q-value is locally stored. A time-division multiplexing module replaces the computed Q-value for the first dimension with at least one Q-value computed for a second dimension at time tn+1. The second dimension is different than the first dimension.
    Type: Application
    Filed: November 11, 2021
    Publication date: March 23, 2023
    Inventors: Sameer Sadashiv PAWANEKAR, Upendra Narayan TRIPATHI