Abstract: An integrated circuit includes a current mode transmitter having a first driver and a second driver. The first driver receives a single bit data stream. The second driver receives a delayed data stream corresponding to the single bit data stream delayed by a clock cycle. The current mode transmitter has a transition detector that generates a bulk modulation signal having a first value when the single bit data stream is the same as the delayed data stream and having a second value when the single bit data stream is different from the delayed data stream. The transition detector supplies the bulk modulation signal to the bulk terminals of driver switches of the first and second drivers.

Abstract: An integrated circuit includes a current mode transmitter. The current mode transmitter includes a first resistor and a second resistor. The resistance of the first resistor is adjusted by measuring the resistance, generating a resistance trimming code based on the measured resistance, and writing the first resistance trimming code to a first register. The resistance of the second resistor is adjusted by generating a second resistance trimming code based on the first resistance trimming code and writing the second resistance trimming code to a second register.

Abstract: A drive circuit includes an input, a driver, a first buffer, a second buffer, a first capacitance element, and a second capacitance element. The driver includes a first PMOS transistor and a first NMOS transistor coupled in series between a supply terminal and a reference terminal. The first buffer is coupled between the input and a control terminal of the first PMOS transistor. The second buffer is coupled between the input and a control terminal of the first NMOS transistor. The first capacitance element is coupled to the control terminal of the first PMOS transistor through a first semiconductor switch. The second capacitance element is coupled to the control terminal of the first NMOS transistor through a second semiconductor switch.

Abstract: A drive circuit includes an input, a driver, a first buffer, a second buffer, a first capacitance element, and a second capacitance element. The driver includes a first PMOS transistor and a first NMOS transistor coupled in series between a supply terminal and a reference terminal. The first buffer is coupled between the input and a control terminal of the first PMOS transistor. The second buffer is coupled between the input and a control terminal of the first NMOS transistor. The first capacitance element is coupled to the control terminal of the first PMOS transistor through a first semiconductor switch. The second capacitance element is coupled to the control terminal of the first NMOS transistor through a second semiconductor switch.

Abstract: A drive circuit includes an input, a driver, a first buffer, a second buffer, a first capacitance element, and a second capacitance element. The driver includes a first PMOS transistor and a first NMOS transistor coupled in series between a supply terminal and a reference terminal. The first buffer is coupled between the input and a control terminal of the first PMOS transistor. The second buffer is coupled between the input and a control terminal of the first NMOS transistor. The first capacitance element is coupled to the control terminal of the first PMOS transistor through a first semiconductor switch. The second capacitance element is coupled to the control terminal of the first NMOS transistor through a second semiconductor switch.

Abstract: In one embodiment, a circuit includes a differential amplifier having a differential pair with a first transistor and second transistor. Each of the first and the second transistors include a front gate contact and a back gate contact. A first digital feedback loop is coupled between an output of the differential amplifier to the back gate contact of the first transistor. A second digital feedback loop is coupled to the back gate contact of the second transistor. The first digital feedback loop is configured to be opposite in phase to the second digital feedback loop.

Abstract: In one embodiment, a circuit includes a differential amplifier having a differential pair with a first transistor and second transistor. Each of the first and the second transistors include a front gate contact and a back gate contact. A first digital feedback loop is coupled between an output of the differential amplifier to the back gate contact of the first transistor. A second digital feedback loop is coupled to the back gate contact of the second transistor. The first digital feedback loop is configured to be opposite in phase to the second digital feedback loop.

Abstract: A buffer includes an input configured to receive a first digital signal having first and second logic states referenced, respectively, to a first high voltage and a first low voltage of a first supply domain. A first inverter circuit includes a pMOS transistor and nMOS transistor having gate terminals connected to the input. A second inverter is connected in series with the output of the first inverter. The second inverter has an output configured to generate a second digital signal having first and second logic states referenced, respectively, to a second high voltage and a second low voltage of a second, different, supply domain, wherein at least the second high voltage is greater than the first high voltage. A feedback circuit is configured to apply the second digital signal as a bias to a transistor body of the p-MOS transistor of the first inverter circuit.

Abstract: A buffer includes an input configured to receive a first digital signal having first and second logic states referenced, respectively, to a first high voltage and a first low voltage of a first supply domain. A first inverter circuit includes a pMOS transistor and nMOS transistor having gate terminals connected to the input. A second inverter is connected in series with the output of the first inverter. The second inverter has an output configured to generate a second digital signal having first and second logic states referenced, respectively, to a second high voltage and a second low voltage of a second, different, supply domain, wherein at least the second high voltage is greater than the first high voltage. A feedback circuit is configured to apply the second digital signal as a bias to a transistor body of the p-MOS transistor of the first inverter circuit.

Abstract: A drive circuit includes an input, a driver, a first buffer, a second buffer, a first capacitance element, and a second capacitance element. The driver includes a first PMOS transistor and a first NMOS transistor coupled in series between a supply terminal and a reference terminal. The first buffer is coupled between the input and a control terminal of the first PMOS transistor. The second buffer is coupled between the input and a control terminal of the first NMOS transistor. The first capacitance element is coupled to the control terminal of the first PMOS transistor through a first semiconductor switch. The second capacitance element is coupled to the control terminal of the first NMOS transistor through a second semiconductor switch.