Patents by Inventor Sameer Wadhwa
Sameer Wadhwa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170059699Abstract: An apparatus, such as a pixel sensor for an ultrasonic imaging apparatus, is disclosed. The apparatus includes a first metallization layer coupled to a piezoelectric layer, wherein a first voltage is formed at the first metallization layer in response to an ultrasonic wave reflecting off an item-to-be-imaged (e.g., a user's fingerprint) and propagating through the piezoelectric layer, and wherein the first metallization layer is situated above a substrate; a second metallization layer situated between the first metallization layer and the substrate; and a device configured to apply a second voltage to the second metallization layer to reduce a parasitic capacitance between the first metallization layer and the substrate.Type: ApplicationFiled: September 1, 2015Publication date: March 2, 2017Inventors: Lennart Karl-Axel Mathe, Sameer Wadhwa, Lingli Xia
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Patent number: 9473165Abstract: Reducing signal dependence for a reference voltage of a CDAC includes: splitting a decoupling capacitor into a plurality of capacitors smaller in size than a size of the decoupling capacitor; isolating at least one of the plurality of capacitors from a sampling buffer coupled to the reference voltage during a conversion phase; and supplying an appropriate amount of charge needed to replenish charge drawn by capacitors in the CDAC at each conversion step using a charge pump to pump in a dummy charge to the CDAC so that resulting configurations of the CDAC draw substantially similar amount of charge for each code change of the each conversion step.Type: GrantFiled: August 21, 2014Date of Patent: October 18, 2016Assignee: QUALCOMM IncorporatedInventors: Seyed Arash Mirhaj, Sameer Wadhwa, Dinesh Jagannath Alladi, Kentaro Yamamoto, Xiaoke Wen, Masoud Ensafdaran, Weihua Chen
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Publication number: 20160056833Abstract: Reducing signal dependence for a reference voltage of a CDAC includes: splitting a decoupling capacitor into a plurality of capacitors smaller in size than a size of the decoupling capacitor; isolating at least one of the plurality of capacitors from a sampling buffer coupled to the reference voltage during a conversion phase; and supplying an appropriate amount of charge needed to replenish charge drawn by capacitors in the CDAC at each conversion step using a charge pump to pump in a dummy charge to the CDAC so that resulting configurations of the CDAC draw substantially similar amount of charge for each code change of the each conversion step.Type: ApplicationFiled: August 21, 2014Publication date: February 25, 2016Inventors: Seyed Arash Mirhaj, Sameer Wadhwa, Dinesh Jagannath Alladi, Kentaro Yamamoto, Xiaoke Wen, Masoud Ensafdaran, Weihua Chen
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Patent number: 8975974Abstract: A wide frequency, low voltage oscillator includes multiple delay elements, in which each delay element includes two inverters coupled through a latching element into a differential-type configuration. Two current-source PMOS devices bias the latching element in a high-gain region at low-voltage. By coupling these current-source PMOS devices into the delay elements, the start-up voltage of the latching element is reduced. Each delay element is also biased using a replica bias circuit that scales the supply/control voltage of the oscillator and provides the scaled supply/control voltage to control the lower rail of oscillation amplitude. By coupling the replica bias circuit to the lower rail, the lower rail of the oscillation amplitude follows the changes to the supply/control voltage.Type: GrantFiled: March 1, 2012Date of Patent: March 10, 2015Assignee: QUALCOMM IncorporatedInventor: Sameer Wadhwa
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Patent number: 8742815Abstract: Temperature-independent delay elements and oscillators are disclosed. In one design, an apparatus includes at least one delay element, a bias circuit, and a current source. The delay element(s) receive a charging current from the current source and provide a delay that is dependent on the charging current. Each delay element may be a current-starved delay element. The delay element(s) may be coupled in series to implement a delay line or in a loop to implement an oscillator. The bias circuit controls generation of the charging current based on a function of at least one parameter (e.g., a switching threshold voltage) of the at least one delay element in order to reduce variations in delay with temperature. The current source provides the charging current for the delay element(s) and is controlled by the bias circuit.Type: GrantFiled: June 20, 2012Date of Patent: June 3, 2014Assignee: QUALCOMM IncorporatedInventors: Sameer Wadhwa, Marzio Pedrali-Noy
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Publication number: 20130342256Abstract: Temperature-independent delay elements and oscillators are disclosed. In one design, an apparatus includes at least one delay element, a bias circuit, and a current source. The delay element(s) receive a charging current from the current source and provide a delay that is dependent on the charging current. Each delay element may be a current-starved delay element. The delay element(s) may be coupled in series to implement a delay line or in a loop to implement an oscillator. The bias circuit controls generation of the charging current based on a function of at least one parameter (e.g., a switching threshold voltage) of the at least one delay element in order to reduce variations in delay with temperature. The current source provides the charging current for the delay element(s) and is controlled by the bias circuit.Type: ApplicationFiled: June 20, 2012Publication date: December 26, 2013Inventors: Sameer Wadhwa, Marzio Pedrali-Noy
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Patent number: 8570108Abstract: An injection-locked oscillator circuit includes a master oscillator, a slave oscillator, and an injection lock control circuit. The slave oscillator is decoupled from the master oscillator (for example, due to an unlock condition). When the slave is free running, its oscillating frequency is adjusted (for example, as a function of a supply voltage). After an amount of time, the slave is to be relocked to the master (for example, due the unlock condition no longer being present). The slave oscillating frequency is made to be slightly lower than the master oscillating frequency. The slave is then only recoupled to the master upon detection of an opposite-phase condition between the master oscillator output signal and the slave oscillator output signal. By only recoupling the slave to the master during opposite-phase conditions, frequency overshoots in the slave oscillating frequency are avoided that may otherwise occur were the recoupling done during in-phase conditions.Type: GrantFiled: August 5, 2011Date of Patent: October 29, 2013Assignee: QUALCOMM IncorporatedInventors: Ashwin Ragunathan, Marzio Pedrali-Noy, Sameer Wadhwa
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Patent number: 8531172Abstract: Power efficient power supply regulator circuits are disclosed. The circuits are configured to modify their overhead current according to current load. This is particularly advantageous for use in display devices with widely varying current loads. Such displays include bi-stable displays, such as interferometric modulation displays, LCD displays, and DMD displays.Type: GrantFiled: October 29, 2012Date of Patent: September 10, 2013Assignee: QUALCOMM MEMS Technologies, Inc.Inventor: Sameer Wadhwa
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Publication number: 20130229238Abstract: A wide frequency, low voltage oscillator includes multiple delay elements, in which each delay element includes two inverters coupled through a latching element into a differential-type configuration. Two current-source PMOS devices bias the latching element in a high-gain region at low-voltage. By coupling these current-source PMOS devices into the delay elements, the start-up voltage of the latching element is reduced. Each delay element is also biased using a replica bias circuit that scales the supply/control voltage of the oscillator and provides the scaled supply/control voltage to control the lower rail of oscillation amplitude. By coupling the replica bias circuit to the lower rail, the lower rail of the oscillation amplitude follows the changes to the supply/control voltage.Type: ApplicationFiled: March 1, 2012Publication date: September 5, 2013Applicant: QUALCOMM IncorporatedInventor: Sameer Wadhwa
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Publication number: 20130106390Abstract: A curvature-compensated band-gap voltage reference circuit includes an operational amplifier and a high-frequency gain stage coupled to an output of the operational amplifier. The circuit also includes an electronic device and a matching circuit.Type: ApplicationFiled: November 1, 2011Publication date: May 2, 2013Applicant: QUALCOMM IncorporatedInventor: Sameer Wadhwa
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Patent number: 8380138Abstract: Closed-loop techniques for adjusting the duty cycle of a cyclical signal, e.g., a clock signal, to approach a target value. In an exemplary embodiment, a charge pump is coupled to a charge and sample module, which drives a de-skew circuit in a negative feedback loop. The charge and sample module couples the charge pump to the integration capacitor during two of four successive phases, and also couples the integration capacitor to sampling capacitors during the other two of the four successive phases. The voltages across the sampling capacitors may be used to control the de-skew circuit, which adjusts the duty cycle of a cyclical signal to be adjusted.Type: GrantFiled: October 21, 2009Date of Patent: February 19, 2013Assignee: Qualcomm IncorporatedInventors: Sameer Wadhwa, Marzio Pedrali-Noy
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Publication number: 20130033331Abstract: An injection-locked oscillator circuit includes a master oscillator, a slave oscillator, and an injection lock control circuit. The slave oscillator is decoupled from the master oscillator (for example, due to an unlock condition). When the slave is free running, its oscillating frequency is adjusted (for example, as a function of a supply voltage). After an amount of time, the slave is to be relocked to the master (for example, due the unlock condition no longer being present). The slave oscillating frequency is made to be slightly lower than the master oscillating frequency. The slave is then only recoupled to the master upon detection of an opposite-phase condition between the master oscillator output signal and the slave oscillator output signal. By only recoupling the slave to the master during opposite-phase conditions, frequency overshoots in the slave oscillating frequency are avoided that may otherwise occur were the recoupling done during in-phase conditions.Type: ApplicationFiled: August 5, 2011Publication date: February 7, 2013Applicant: QUALCOMM IncorporatedInventors: Ashwin RAGHUNATHAN, Marzio Pedrali-Noy, Sameer Wadhwa
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Patent number: 8362848Abstract: A supply-regulated VCO exhibits reduced or no supply sensitivity peaking. The VCO includes an oscillator whose supply current is regulated to control the oscillating frequency of the oscillator. A VCO input signal controls the supply current so that there is a relationship between the input signal and the oscillator output frequency. Power supply noise that might otherwise affect oscillator operation is shunted from a supply current input lead of the oscillator to ground by a bypass capacitor. In one example, an auxiliary circuit supplies an auxiliary supply current to the oscillator, thereby reducing the amount of supply current a supply regulation control loop circuit must supply. In another example, a supply regulation control loop circuit supplies a control current to a main oscillator, but the bypass capacitor is not coupled to this oscillator but rather is coupled to a slave oscillator that is injection locked to the main oscillator.Type: GrantFiled: April 7, 2011Date of Patent: January 29, 2013Assignee: QUALCOMM IncorporatedInventors: Ashwin Raghunathan, Marzio Pedrali-Noy, Sameer Wadhwa
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Patent number: 8330511Abstract: A charge pump includes an UP current mirror and a DN current mirror. The UP current mirror is controlled by an input UP signal and supplies charge onto an output node. The DN current mirror is controlled by an input DN signal and draws charge from the output node. The input UP and DN signals may be received from a phase detector in a Phase-Locked Loop (PLL). To prevent disturbances on bias nodes of the UP and DN current mirrors that otherwise might occur, replica circuits of portions of the UP and DN current mirrors are provided. Each replica circuit is coupled to a bias node of a corresponding current mirror, but is controlled by an input signal of opposite polarity to the input signal that controls the current mirror so that the replica circuit creates disturbances that tend to counteract disturbances created by switching of the current mirror.Type: GrantFiled: April 20, 2010Date of Patent: December 11, 2012Assignee: QUALCOMM IncorporatedInventors: Ashwin Raghunathan, Sameer Wadhwa, Marzio Pedrali-Noy
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Patent number: 8305056Abstract: A low drop-out (LDO) voltage regulator with a wide bandwidth power supply rejection ratio (PSRR) is described. In one aspect, the LDO voltage regulator includes two individual voltage regulator circuit stages. A first stage voltage regulator circuit output is at an intermediate voltage (VINT) between an input supply voltage (VDD) and a final regulated output voltage (VREG). A second stage voltage regulator circuit output is at the final regulated output voltage (VREG) and is optimized for noise-sensitive analog circuits across a wide operating bandwidth. The first stage voltage regulator circuit has a zero frequency while the second stage voltage regulator circuit has a matching pole frequency to minimize the AC response from VDD to VREG across all frequencies.Type: GrantFiled: December 9, 2008Date of Patent: November 6, 2012Assignee: Qualcomm IncorporatedInventor: Sameer Wadhwa
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Patent number: 8299774Abstract: Power efficient power supply regulator circuits are disclosed. The circuits are configured to modify their overhead current according to current load. This is particularly advantageous for use in display devices with widely varying current loads. Such displays include bi-stable displays, such as interferometric modulation displays, LCD displays, and DMD displays.Type: GrantFiled: June 20, 2011Date of Patent: October 30, 2012Assignee: Qualcomm Mems Technologies, Inc.Inventor: Sameer Wadhwa
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Publication number: 20120256693Abstract: A supply-regulated VCO exhibits reduced or no supply sensitivity peaking. The VCO includes an oscillator whose supply current is regulated to control the oscillating frequency of the oscillator. A VCO input signal controls the supply current so that there is a relationship between the input signal and the oscillator output frequency. Power supply noise that might otherwise affect oscillator operation is shunted from a supply current input lead of the oscillator to ground by a bypass capacitor. In one example, an auxiliary circuit supplies an auxiliary supply current to the oscillator, thereby reducing the amount of supply current a supply regulation control loop circuit must supply. In another example, a supply regulation control loop circuit supplies a control current to a main oscillator, but the bypass capacitor is not coupled to this oscillator but rather is coupled to a slave oscillator that is injection locked to the main oscillator.Type: ApplicationFiled: April 7, 2011Publication date: October 11, 2012Applicant: QUALCOMM INCORPORATEDInventors: Ashwin Raghunathan, Marzio Pedrali-Noy, Sameer Wadhwa
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Publication number: 20110254828Abstract: Power efficient power supply regulator circuits are disclosed. The circuits are configured to modify their overhead current according to current load. This is particularly advantageous for use in display devices with widely varying current loads. Such displays include bi-stable displays, such as interferometric modulation displays, LCD displays, and DMD displays.Type: ApplicationFiled: June 20, 2011Publication date: October 20, 2011Applicant: QUALCOMM MEMS Technologies, Inc.Inventor: Sameer Wadhwa
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Publication number: 20110254615Abstract: A charge pump includes an UP current mirror and a DN current mirror. The UP current mirror is controlled by an input UP signal and supplies charge onto an output node. The DN current mirror is controlled by an input DN signal and draws charge from the output node. The input UP and DN signals may be received from a phase detector in a Phase-Locked Loop (PLL). To prevent disturbances on bias nodes of the UP and DN current mirrors that otherwise might occur, replica circuits of portions of the UP and DN current mirrors are provided. Each replica circuit is coupled to a bias node of a corresponding current mirror, but is controlled by an input signal of opposite polarity to the input signal that controls the current mirror so that the replica circuit creates disturbances that tend to counteract disturbances created by switching of the current mirror.Type: ApplicationFiled: April 20, 2010Publication date: October 20, 2011Applicant: QUALCOMM INCORPORATEDInventors: Ashwin Raghunathan, Sameer Wadhwa, Marzio Pedrali-Noy
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Patent number: 7977931Abstract: Power efficient power supply regulator circuits are disclosed. The circuits are configured to modify their overhead current according to current load. This is particularly advantageous for use in display devices with widely varying current loads. Such displays include bi-stable displays, such as interferometric modulation displays, LCD displays, and DMD displays.Type: GrantFiled: March 18, 2008Date of Patent: July 12, 2011Assignee: QUALCOMM MEMS Technologies, Inc.Inventor: Sameer Wadhwa