Patents by Inventor Sameh S. Rezeq
Sameh S. Rezeq has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9020454Abstract: An apparatus and method of linearization of a digitally-controlled pre-power amplifier (DPA) and RF power amplifier (PA) for performing predistortion calibration to compensate for nonlinearlities in the DPA and PA circuits. A predistortion look up table (LUT) stores measured distortion compensation data that is applied to the TX data before being input to the digital-to-frequency converter (DFC), DPA and PA. The on-chip receiver, which is normally inactive during the TX burst in a half-duplex operation, demodulates the RF PA output and uses the digital I/Q RX outputs to perform calibration of the TX pre-distortion tables. A sample of the RF output signal is provided to the receiver chain. While the PA (DPA) code is increasing (or decreasing), the amplitude and phase of the recovered I/Q samples are used to determine the instantaneous value of the AM/AM and AM/PM pre-distortion from which an update to the predistortion tables may be computed.Type: GrantFiled: May 25, 2012Date of Patent: April 28, 2015Assignee: Texas Instruments IncorporatedInventors: Khurram Waheed, Robert B. Staszewski, Sameh S. Rezeq, Oren E. Eliezer
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Publication number: 20120263256Abstract: An apparatus and method of linearization of a digitally-controlled pre-power amplifier (DPA) and RF power amplifier (PA) for performing predistortion calibration to compensate for nonlinearlities in the DPA and PA circuits. A predistortion look up table (LUT) stores measured distortion compensation data that is applied to the TX data before being input to the digital-to-frequency converter (DFC), DPA and PA. The on-chip receiver, which is normally inactive during the TX burst in a half-duplex operation, demodulates the RF PA output and uses the digital I/Q RX outputs to perform calibration of the TX pre-distortion tables. A sample of the RF output signal is provided to the receiver chain. While the PA (DPA) code is increasing (or decreasing), the amplitude and phase of the recovered I/Q samples are used to determine the instantaneous value of the AM/AM and AM/PM pre-distortion from which an update to the predistortion tables may be computed.Type: ApplicationFiled: May 25, 2012Publication date: October 18, 2012Inventors: Khurram Waheed, Robert B. Staszewski, Sameh S. Rezeq, Oren E. Eliezer
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Patent number: 8195103Abstract: A novel apparatus and method of linearization of a digitally controlled pre-power amplifier (DPA) and RF power amplifier (PA). The mechanism is operative to perform predistortion calibration to compensate for nonlinearities in the DPA and PA circuits. A predistortion look up table (LUT) stores measured distortion compensation data that is applied to the TX data before being input to the digital to frequency converter (DFC), DPA and PA. The mechanism of the invention takes advantage of the on-chip receiver, which is normally inactive during the TX burst in a half-duplex operation, to demodulate the RF PA output and use the digital I/Q RX outputs to perform calibration of the TX pre-distortion tables. Controlled RF coupling is used to provide a sample of the RF output signal that to the receiver chain. The contents of the predistortion LUT are typically updated during the PA power up or down ramp.Type: GrantFiled: February 15, 2007Date of Patent: June 5, 2012Assignee: Texas Instruments IncorporatedInventors: Khurram Waheed, Robert B. Staszewski, Sameh S. Rezeq, Oren E. Eliezer
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Patent number: 8170507Abstract: Predistortion methods and apparatus for transmitter linearization in a communication transceiver are disclosed.Type: GrantFiled: October 29, 2008Date of Patent: May 1, 2012Assignee: Texas Instruments IncorporatedInventors: Yongtao Wang, Khurram Waheed, Sameh S. Rezeq, Jaimin Mehta, Prasad Srinivasan, Khurram Muhammad
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Patent number: 7817747Abstract: A novel apparatus for and method of delay alignment between amplitude and phase/frequency modulation paths in a digital polar transmitter. The invention provides a fully digital delay alignment mechanism where better than nanosecond alignment is achieved by accounting for processing delays in the digital circuit modules of the transmitter and by the use of programmable delay elements spread across several clock domains. Tapped delay lines compensate for propagation and settling delays in analog elements such as the DCO, dividers, quad switch, buffers, level shifters and digital pre-power amplifier (DPA). A signal correlative mechanism is provided whereby data from the amplitude and phase/frequency modulation paths to be matched is first interpolated and then cross-correlated to achieve accuracy better than the clock domain of comparison.Type: GrantFiled: February 15, 2007Date of Patent: October 19, 2010Assignee: Texas Instruments IncorporatedInventors: Khurram Waheed, Jayawardan Janardhanan, Sameh S. Rezeq, Robert B. Staszewski, Saket Jalan
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Patent number: 7787563Abstract: A transmitter employing a sigma delta modulator having a noise transfer function adapted to shift quantization noise outside at least one frequency band of interest. A technique is presented to synthesize the controllers within a single-loop sigma delta modulator such that the noise transfer function can be chosen arbitrarily from a family of functions satisfying certain conditions. Using the novel modulator design technique, polar and Cartesian (i.e. quadrature) transmitter structures are supported. A transmitter employing polar transmit modulation is presented that shapes the spectral emissions of the digitally-controlled power amplifier such that they are significantly and sufficiently attenuated in one or more desired frequency bands. Similarly, a transmitter employing Cartesian transmit modulation is presented that shapes the spectral emissions of a hybrid power amplifier such that they are significantly and sufficiently attenuated in one or more desired frequency bands.Type: GrantFiled: December 7, 2005Date of Patent: August 31, 2010Assignee: Texas Instruments IncorporatedInventors: Nir Tal, Sameh S. Rezeq, Robert B. Staszewski, Oren E. Eliezer, Ofer Friedman
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Publication number: 20100188148Abstract: A novel and useful apparatus for and method of predistortion compensation of device (e.g., transistor) mismatch in a digital power amplifier (DPA). The device mismatch predistortion mechanism of the present invention addresses the problem of matching between two types of binary weighted transistors, whereby mismatched transistors cause degradation in wideband noise. The invention provides a digital predistortion mechanism which functions to pre-distort the mismatch ratio based on a data table calculated a priori enabling a polar transmitter to meet output spectrum and error vector magnitude (EVM) requirements of the particular modern wideband wireless standard, such as GSM, 3G WCDMA, etc.Type: ApplicationFiled: January 26, 2009Publication date: July 29, 2010Inventors: Jaimin A. Mehta, Sameh S. Rezeq, Manouchehr Entezari, Robert B. Staszewski
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Publication number: 20100135368Abstract: A novel and useful apparatus for and method of upsampling/interpolating a discrete-time input sample stream with time alignment utilizing the addition of randomized high frequency noise. The upsampling mechanism is an effective implementation of a second order interpolator that eliminates the need for a conventional filter as the filtering action is effectively built into the mechanism. The upsampling mechanism takes the derivative of the discrete-time input sample stream, thereby effectively providing another order of interpolation over a conventional interpolator. Before outputting the interpolated signal, an integrator takes the integral of the interpolated samples. Any processing performed between the derivative and integrator blocks effectively provides an additional order of interpolation. High frequency noise (i.e. dithering) is added to the differentiated samples in order to eliminate the spectral regrowth spurs that would otherwise appear in the output after rounding.Type: ApplicationFiled: December 2, 2008Publication date: June 3, 2010Inventors: Jaimin A. Mehta, Sameh S. Rezeq, Manouchehr Entezari, Robert B. Staszewski
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Patent number: 7715490Abstract: A novel sigma delta amplitude modulator having a noise transfer function adapted to shift quantization noise outside at least one frequency band of interest. In one embodiment, the sigma delta amplitude modulator includes a programmable order low pass stage. In a second embodiment, the sigma delta amplitude modulator incorporates comb filtering wherein each comb filter comprises a plurality of fingers to permit greater programmability in the frequency location of notches. A polar transmitter incorporating the sigma delta amplitude modulator is presented that shapes the spectral emissions of the digitally-controlled power amplifier such that they are significantly and sufficiently attenuated in one or more desired frequency bands.Type: GrantFiled: March 8, 2006Date of Patent: May 11, 2010Assignee: Texas Instruments IncorporatedInventor: Sameh S. Rezeq
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Publication number: 20100105338Abstract: Predistortion methods and apparatus for transmitter linearization in a communication transceiver are disclosed.Type: ApplicationFiled: October 29, 2008Publication date: April 29, 2010Inventors: Yongtao Wang, Khurram Waheed, Sameh S. Rezeq, Jaimin Mehta, Prasad Srinivasan, Khurram Muhammad
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Patent number: 7405685Abstract: A novel method and apparatus for a negative contributive offset compensation mechanism for a transmit buffer adapted to compensate for the positive offset generated by higher order sigma-delta modulators used to amplitude modulate the transmit buffer. The positive outputs from the sigma-delta modulator are processed differently than the negative outputs. The inverters associated with the negative outputs in the sigma-delta modulator are removed and the clock signal used to drive the transistors corresponding to the negative outputs is negated or shifted 180 degrees from the clock used to drive the transistors corresponding to the positive outputs. A non-inverted version of the clock is used with the positive outputs and an inverse clock is used with the negative outputs. Use of the inverse clock causes a negative contributive offset to be generated that is added on the second half cycle of each clock. The result is an offset compensated RF output signal having zero offset.Type: GrantFiled: July 11, 2005Date of Patent: July 29, 2008Assignee: Texas Instruments IncorporatedInventors: Sameh S. Rezeq, Dirk Leipold, Robert B. Staszewski, Chih-Ming Hung
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Publication number: 20070190952Abstract: A novel apparatus and method of linearization of a digitally controlled pre-power amplifier (DPA) and RF power amplifier (PA). The mechanism is operative to perform predistortion calibration to compensate for nonlinearities in the DPA and PA circuits. A predistortion look up table (LUT) stores measured distortion compensation data that is applied to the TX data before being input to the digital to frequency converter (DFC), DPA and PA. The mechanism of the invention takes advantage of the on-chip receiver, which is normally inactive during the TX burst in a half-duplex operation, to demodulate the RF PA output and use the digital I/Q RX outputs to perform calibration of the TX pre-distortion tables. Controlled RF coupling is used to provide a sample of the RF output signal that to the receiver chain. The contents of the predistortion LUT are typically updated during the PA power up or down ramp.Type: ApplicationFiled: February 15, 2007Publication date: August 16, 2007Inventors: Khurram Waheed, Robert B. Staszewski, Sameh S. Rezeq, Oren E. Eliezer
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Publication number: 20070189417Abstract: A novel apparatus for and method of delay alignment between amplitude and phase/frequency modulation paths in a digital polar transmitter. The invention provides a fully digital delay alignment mechanism where better than nanosecond alignment is achieved by accounting for processing delays in the digital circuit modules of the transmitter and by the use of programmable delay elements spread across several clock domains. Tapped delay lines compensate for propagation and settling delays in analog elements such as the DCO, dividers, quad switch, buffers, level shifters and digital pre-power amplifier (DPA). A signal correlative mechanism is provided whereby data from the amplitude and phase/frequency modulation paths to be matched is first interpolated and then cross-correlated to achieve accuracy better than the clock domain of comparison.Type: ApplicationFiled: February 15, 2007Publication date: August 16, 2007Inventors: Khurram Waheed, Jayawardan Janardhanan, Sameh S. Rezeq, Robert B. Staszewski, Saket Jalan