Abstract: A digitally selectable power gate with thermometer-encoded upper bits may provide solutions for problems digital power gate-based regulators. These solutions may include the use of a fully binary power gate, either in structure or by local decoding of binary control signal to an addressable row-based power gate. This provides improved performance over a row-based code rotation, which is intended to avoid instantaneous overheating of power gate devices but may not mitigate aging effects. Another solution includes ganging a primary DLVR and one or more secondaries. The primary DLVR may include a voltage sense and active controller, which may forward its PG code to secondary instances. Therm and current sensor rotation may be performed locally at the secondaries and a current monitor data may be rolled up from all ganged DLVRs.

Abstract: A reduced-size replica of power gate transistors may be used within a closed-loop voltage regulator to measure the average current delivered by the transistors in the non-replica power gate. The measured current is compared against a known reference current, and a feedback loop is used to modify the gate bias of the power gate and replica power gate transistors. An improved current sensing power gate replica solution may include measuring current from a small replica of the power gate and extrapolating the total current by digitally multiplying the replica current by the ratio of the size of the enabled power gates to the size of the replicas. The current through the replicas, which substantially matches the current in equivalent power gate devices, may be collected on an analog bus and conducted across a known resistor to generate a voltage that determines an estimated current of the power gate devices.

Abstract: Described is an apparatus which comprises: an asynchronous clock generator to generate an asynchronous clock signal; a digital sampler for sampling a signal using the asynchronous clock signal; a duty cycle corrector (DCC) to receive a differential input clock and to generate a differential output clock, wherein the digital sampler to sample at least one of an output clock from the differential output clock; and a counter to count output of the digital sampler and to provide a control to the DCC to adjust duty cycle of the differential output clock.

Abstract: Macro-transistor structures are disclosed. In some cases, the macro-transistor structures have the same number of terminals and properties similar to long-channel transistors, but are suitable for analog circuits in deep-submicron technologies at deep-submicron process nodes. The macro-transistor structures can be implemented, for instance, with a plurality of transistors constructed and arranged in series, and with their gates tied together, generally referred to herein as a transistor stack. One or more of the serial transistors within the stack can be implemented with a plurality of parallel transistors and/or can have a threshold voltage that is different from the threshold voltages of other transistors in the stack. Alternatively, or in addition, one or more of the serial transistors within the macro-transistor can be statically or dynamically controlled to tune the performance characteristics of the macro-transistor.

Abstract: Macro-transistor structures are disclosed. In some cases, the macro-transistor structures have the same number of terminals and properties similar to long-channel transistors, but are suitable for analog circuits in deep-submicron technologies at deep-submicron process nodes. The macro-transistor structures can be implemented, for instance, with a plurality of transistors constructed and arranged in series, and with their gates tied together, generally referred to herein as a transistor stack. One or more of the serial transistors within the stack can be implemented with a plurality of parallel transistors and/or can have a threshold voltage that is different from the threshold voltages of other transistors in the stack. Alternatively, or in addition, one or more of the serial transistors within the macro-transistor can be statically or dynamically controlled to tune the performance characteristics of the macro-transistor.

Abstract: Macro-transistor structures are disclosed. In some cases, the macro-transistor structures have the same number of terminals and properties similar to long-channel transistors, but are suitable for analog circuits in deep-submicron technologies at deep-submicron process nodes. The macro-transistor structures can be implemented, for instance, with a plurality of transistors constructed and arranged in series, and with their gates tied together, generally referred to herein as a transistor stack. One or more of the serial transistors within the stack can be implemented with a plurality of parallel transistors and/or can have a threshold voltage that is different from the threshold voltages of other transistors in the stack. Alternatively, or in addition, one or more of the serial transistors within the macro-transistor can be statically or dynamically controlled to tune the performance characteristics of the macro-transistor.

Abstract: Described is an apparatus which comprises: an amplifier; a first set of samplers to sample data output from the amplifier according to a clock signal, the set of samplers to generate an output; and a converter to convert the output of the first set of samplers to 1 -hot encoded data.

Abstract: Described is an apparatus which comprises: an amplifier; a first set of samplers to sample data output from the amplifier according to a clock signal, the set of samplers to generate an output; and a converter to convert the output of the first set of samplers to 1 -hot encoded data.

Abstract: Described is an apparatus which comprises: an asynchronous clock generator to generate an asynchronous clock signal; a digital sampler for sampling a signal using the asynchronous clock signal; a duty cycle corrector (DCC) to receive a differential input clock and to generate a differential output clock, wherein the digital sampler to sample at least one of an output clock from the differential output clock; and a counter to count output of the digital sampler and to provide a control to the DCC to adjust duty cycle of the differential output clock.

Abstract: Described herein is an apparatus and system of an electrostatic discharge circuit. The apparatus comprises: a clamp transistor with a terminal coupled to a node with a power supply; and a detector to determine when the power supply crosses a first threshold, the detector to generate a trigger signal to cause the clamp transistor to remain off when the power supply on the node is below the first threshold.

Abstract: Macro-transistor structures are disclosed. In some cases, the macro-transistor structures have the same number of terminals and properties similar to long-channel transistors, but are suitable for analog circuits in deep submicron technologies deep-submicron process nodes. The macro-transistor structures can be implemented, for instance, with a plurality of transistors constructed and arranged in series, and with their gates tied together, generally referred to herein as a transistor stack. One or more of the serial transistors within the stack can be implemented with a plurality of parallel transistors and/or can have a threshold voltage different that is different from the threshold voltages of other transistors in the stack. Alternatively, or in addition, one or more of the serial transistors within the macro-transistor can be statically or dynamically controlled to tune the performance characteristics of the macro-transistor.

Abstract: Described herein is an apparatus and system of an electrostatic discharge circuit. The apparatus comprises: a clamp transistor with a terminal coupled to a node with a power supply; and a detector to determine when the power supply crosses a first threshold, the detector to generate a trigger signal to cause the clamp transistor to remain off when the power supply on the node is below the first threshold.

Abstract: An amplitude detection circuit using a sinusoidal input signal inputs to produce a digital output (a one or zero) is described. The circuit uses an input field effect transistor (FET) with a gate load coupled to a gate of the input FET. A drain load may be coupled to a drain of the input FET. A source load may be coupled to a source of the input FET. A controllable variable current generator provides a current to the source of the input FET, biasing the source of the input FET to a reference voltage. An input signal conductor may be coupled to the gate of the input FET. Other embodiments are described.

Abstract: Methods and systems to controllably steer multiple phases of a differential signal, including to generate a differential current in response to a differential voltage, to controllably steer the differential current between multiple output circuits in response to corresponding control signals, which may be out of phase with respect to one another, and to generate multiple corresponding outputs corresponding to the multiple steered phases of the current. A differential input circuit and a current steering circuit may be common to multiple output circuits, and a common offset compensation may be provided to compensate for a substantial portion of offset associated with the multiple outputs.

Abstract: Methods and systems to controllably steer multiple phases of a differential signal, including to generate a differential current in response to a differential voltage, to controllably steer the differential current between multiple output circuits in response to corresponding control signals, which may be out of phase with respect to one another, and to generate multiple corresponding outputs corresponding to the multiple steered phases of the current. A differential input circuit and a current steering circuit may be common to multiple output circuits, and a common offset compensation may be provided to compensate for a substantial portion of offset associated with the multiple outputs.

Abstract: An amplitude detection circuit using a sinusoidal input signal inputs to produce a digital output (a one or zero) is described. The circuit uses an input field effect transistor (FET) with a gate load coupled to a gate of the input FET. A drain load may be coupled to a drain of the input FET. A source load may be coupled to a source of the input FET. A controllable variable current generator provides a current to the source of the input FET, biasing the source of the input FET to a reference voltage. An input signal conductor may be coupled to the gate of the input FET. Other embodiments are described.

Abstract: Disclosed herein are embodiments of an LC-type VCO with multiple operational frequency bands having reasonably similar frequency vs. control signal slopes.