Patents by Inventor Samudyatha Chakki

Samudyatha Chakki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Selecting a low power state based on cache flush latency determination
    Patent number: 10963038
    Abstract: In an embodiment, a processor includes a plurality of cores to independently execute instructions, a shared cache coupled to the cores and including a plurality of lines to store data, and a power controller including a low power control logic to calculate a flush latency to flush the shared cache based on a state of the plurality of lines. Other embodiments are described and claimed.
    Type: Grant
    Filed: January 21, 2019
    Date of Patent: March 30, 2021
    Assignee: Intel Corporation
    Inventors: Sundar Ramani, Arvind Raman, Arvind Mandhani, Ashish V. Choubal, Kalyan Muthukumar, Ajaya V. Durg, Samudyatha Chakki
  • Selecting A Low Power State Based On Cache Flush Latency Determination
    Publication number: 20190155370
    Abstract: In an embodiment, a processor includes a plurality of cores to independently execute instructions, a shared cache coupled to the cores and including a plurality of lines to store data, and a power controller including a low power control logic to calculate a flush latency to flush the shared cache based on a state of the plurality of lines. Other embodiments are described and claimed.
    Type: Application
    Filed: January 21, 2019
    Publication date: May 23, 2019
    Inventors: Sundar Ramani, Arvind Raman, Arvind Mandhani, Ashish V. Choubal, Kalyan Muthukumar, Ajaya V. Durg, Samudyatha Chakki
  • Selecting a low power state based on cache flush latency determination
    Patent number: 10198065
    Abstract: In an embodiment, a processor includes a plurality of cores to independently execute instructions, a shared cache coupled to the cores and including a plurality of lines to store data, and a power controller including a low power control logic to calculate a flush latency to flush the shared cache based on a state of the plurality of lines. Other embodiments are described and claimed.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: February 5, 2019
    Assignee: Intel Corporation
    Inventors: Sundar Ramani, Arvind Raman, Arvind Mandhani, Ashish V. Choubal, Kalyan Muthukumar, Ajaya V. Durg, Samudyatha Chakki
  • Selecting A Low Power State Based On Cache Flush Latency Determination
    Publication number: 20170228014
    Abstract: In an embodiment, a processor includes a plurality of cores to independently execute instructions, a shared cache coupled to the cores and including a plurality of lines to store data, and a power controller including a low power control logic to calculate a flush latency to flush the shared cache based on a state of the plurality of lines. Other embodiments are described and claimed.
    Type: Application
    Filed: April 24, 2017
    Publication date: August 10, 2017
    Inventors: Sundar Ramani, Arvind Raman, Arvind Mandhani, Ashish V. Choubal, Kalyan Muthukumar, Ajaya V. Durg, Samudyatha Chakki
  • Selecting a low power state based on cache flush latency determination
    Patent number: 9665153
    Abstract: In an embodiment, a processor includes a plurality of cores to independently execute instructions, a shared cache coupled to the cores and including a plurality of lines to store data, and a power controller including a low power control logic to calculate a flush latency to flush the shared cache based on a state of the plurality of lines. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: May 30, 2017
    Assignee: Intel Corporation
    Inventors: Sundar Ramani, Arvind Raman, Arvind Mandhani, Ashish V. Choubal, Kalyan Muthukumar, Ajaya V. Durg, Samudyatha Chakki
  • Selecting A Low Power State Based On Cache Flush Latency Determination
    Publication number: 20150268711
    Abstract: In an embodiment, a processor includes a plurality of cores to independently execute instructions, a shared cache coupled to the cores and including a plurality of lines to store data, and a power controller including a low power control logic to calculate a flush latency to flush the shared cache based on a state of the plurality of lines. Other embodiments are described and claimed.
    Type: Application
    Filed: March 21, 2014
    Publication date: September 24, 2015
    Inventors: Sundar Ramani, Arvind Raman, Arvind Mandhani, Ashish V. Choubal, Kalyan Muthukumar, Ajaya V. Durg, Samudyatha Chakki