Patents by Inventor Samuel Asanbeng Atungsiri
Samuel Asanbeng Atungsiri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Data processing apparatus and method for use in an interleaver suitable for multiple operating modes
Patent number: 9338043Abstract: A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.Type: GrantFiled: April 30, 2015Date of Patent: May 10, 2016Assignee: SONY CORPORATIONInventors: Samuel Asanbeng Atungsiri, Matthew Paul Athol Taylor, John Nicholas Wilson -
DATA PROCESSING APPARATUS AND METHOD FOR USE IN AN INTERLEAVER SUITABLE FOR MULTIPLE OPERATING MODES
Publication number: 20150236879Abstract: A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.Type: ApplicationFiled: April 30, 2015Publication date: August 20, 2015Applicant: Sony CorporationInventors: Samuel Asanbeng ATUNGSIRI, Matthew Paul Athol Taylor, John Nicholas Wilson -
Patent number: 9106494Abstract: A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.Type: GrantFiled: September 16, 2014Date of Patent: August 11, 2015Assignee: SONY CORPORATIONInventors: Jean-Luc Peron, Matthew Paul Athol Taylor, John Nicholas Wilson, Samuel Asanbeng Atungsiri
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Data processing apparatus and method for use in an interleaver suitable for multiple operating modes
Patent number: 9054927Abstract: A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.Type: GrantFiled: November 3, 2014Date of Patent: June 9, 2015Assignee: SONY CORPORATIONInventors: Samuel Asanbeng Atungsiri, Matthew Paul Athol Taylor, John Nicholas Wilson -
DATA PROCESSING APPARATUS AND METHOD FOR USE IN AN INTERLEAVER SUITABLE FOR MULTIPLE OPERATING MODES
Publication number: 20150049838Abstract: A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.Type: ApplicationFiled: November 3, 2014Publication date: February 19, 2015Applicant: Sony CorporationInventors: Samuel Asanbeng ATUNGSIRI, Matthew Paul Athol Taylor, John Nicholas Wilson -
Publication number: 20150003559Abstract: A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.Type: ApplicationFiled: September 16, 2014Publication date: January 1, 2015Applicant: SONY CORPORATIONInventors: Jean-Luc Peron, Matthew Paul Athol Taylor, John Nicholas Wilson, Samuel Asanbeng Atungsiri
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Data processing apparatus and method for use in an interleaver suitable for multiple operating modes
Patent number: 8891691Abstract: A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.Type: GrantFiled: November 12, 2013Date of Patent: November 18, 2014Assignee: Sony CorporationInventors: Samuel Asanbeng Atungsiri, Matthew Paul Athol Taylor, John Nicholas Wilson -
Patent number: 8885761Abstract: A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.Type: GrantFiled: April 9, 2012Date of Patent: November 11, 2014Assignee: Sony CorporationInventors: Jean-Luc Peron, Matthew Paul Athol Taylor, Samuel Asanbeng Atungsiri, John Nicholas Wilson
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DATA PROCESSING APPARATUS AND METHOD FOR USE IN AN INTERLEAVER SUITABLE FOR MULTIPLE OPERATING MODES
Publication number: 20140072081Abstract: A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.Type: ApplicationFiled: November 12, 2013Publication date: March 13, 2014Applicant: Sony CorporationInventors: Samuel Asanbeng ATUNGSIRI, Matthew Paul Athol TAYLOR, John Nicholas WILSON -
Patent number: 8619890Abstract: A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.Type: GrantFiled: September 14, 2012Date of Patent: December 31, 2013Assignee: Sony CorporationInventors: Samuel Asanbeng Atungsiri, Matthew Paul Athol Taylor, John Nicholas Wilson
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Patent number: 8406339Abstract: A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.Type: GrantFiled: February 2, 2012Date of Patent: March 26, 2013Assignee: Sony CorporationInventors: Matthew Paul Athol Taylor, Samuel Asanbeng Atungsiri, John Nicholas Wilson
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Patent number: 8396104Abstract: A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit. The linear feedback shift register has eleven register stages with a generator polynomial for the linear feedback shift register of R?i[10]=R?i?1[0]?R?i?1[2], and the permutation code forms, with an additional bit, a twelve bit address.Type: GrantFiled: February 16, 2012Date of Patent: March 12, 2013Assignee: Sony CorporationInventors: Matthew Paul Athol Taylor, Samuel Asanbeng Atungsiri, John Nicholas Wilson
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Patent number: 8369434Abstract: A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.Type: GrantFiled: November 21, 2011Date of Patent: February 5, 2013Assignee: Sony CorporationInventors: Matthew Paul Athol Taylor, Samuel Asanbeng Atungsiri, John Nicholas Wilson
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Patent number: 8351528Abstract: A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.Type: GrantFiled: February 1, 2012Date of Patent: January 8, 2013Assignee: Sony CorporationInventors: Matthew Paul Athol Taylor, Samuel Asanbeng Atungsiri, John Nicholas Wilson
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Patent number: 8351541Abstract: A data processing apparatus communicates data bits on a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processing apparatus comprises a parity interleaver operable to perform parity interleaving on Low Density Parity Check (LDPC) encoded data bits obtained by performing LDPC encoding according to a parity check matrix of an LDPC code including a parity matrix corresponding to parity bits of the LDPC code, the parity matrix having a stepwise structure, so that a parity bit of the LDPC encoded data bits is interleaved to a different parity bit position. A mapping unit maps the parity interleaved bits onto data symbols corresponding to modulation symbols of a modulation scheme of the OFDM sub-carrier signals.Type: GrantFiled: January 27, 2012Date of Patent: January 8, 2013Assignee: Sony CorporationInventors: Mathew Paul Athol Taylor, Samuel Asanbeng Atungsiri, Takashi Yokokawa, Makiko Yamamoto
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Publication number: 20130003758Abstract: A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.Type: ApplicationFiled: September 14, 2012Publication date: January 3, 2013Applicant: Sony CorporationInventors: Samuel Asanbeng ATUNGSIRI, Matthew Paul Athol Taylor, John Nicholas Wilson
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Publication number: 20120314786Abstract: A transmitter communicating data using Orthogonal Frequency Division Multiplexed (OFDM) symbols including plural sub-carrier symbols in the frequency domain for modulating with data to be carried. The transmitter includes a modulator to receive data symbols from a first data pipe according to a first communications channel, to receive data symbols from a local service insertion data pipe according to a local communications channel, and to modulate the sub-carrier signals of the OFDM symbols with either the data symbols from the first data pipe or from both the first data pipe and the local service insertion pipe; modulation from the first data pipe maps the data symbols is according to a first modulation scheme, and modulation from the first data pipe and the local service insertion pipe maps the data symbols is according to a second modulation scheme.Type: ApplicationFiled: February 22, 2011Publication date: December 13, 2012Applicant: Sony CorporationInventors: Samuel Asanbeng Atungsiri, Lothar Stadelmeier, Sven Muhammad, Jorg Robert, Obioma Chiedozie Donald Okehie, Matthew Paul Athol Taylor, Jan Zoellner
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Patent number: 8320484Abstract: A data processor maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.Type: GrantFiled: December 30, 2011Date of Patent: November 27, 2012Assignee: Sony CorporationInventors: Matthew Paul Athol Taylor, Samuel Asanbeng Atungsiri, John Nicholas Wilson
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Patent number: 8306137Abstract: A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.Type: GrantFiled: October 24, 2008Date of Patent: November 6, 2012Assignee: Sony CorporationInventors: Samuel Asanbeng Atungsiri, Matthew Paul Athol Taylor, John Nicholas Wilson
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Publication number: 20120250777Abstract: A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.Type: ApplicationFiled: April 9, 2012Publication date: October 4, 2012Applicant: Sony Europe LimitedInventors: Jean-Luc PERON, Matthew Paul Athol TAYLOR, Samuel Asanbeng ATUNGSIRI, John Nicholas WILSON