Abstract: A computer system employs DRAM devices in a memory sub-system, which devices are assigned into particular pools corresponding to different power consumption states with a most-recently-accessed (MRA) device being assigned to an active pool and placed at the top of a stack structure. A LRA device in the active pool is evicted from the active pool and placed in a standby pool when the active pool is full and the processor accesses another device, which is not currently assigned to the active pool. A LRA device of the standby pool gets evicted into a nap pool upon one of two conditions: either a timeout occurs, or the standby and active pools are full and the processor accesses another device, which is not currently assigned to either the active or standby pools.