Abstract: An apparatus and method for efficiently managing balanced performance among replicated partitions of an integrated circuit despite loss of functionality due to manufacturing defects. A processing unit includes at least two replicated partitions, each assigned to operation parameters of a respective power domain. The partitions include multiple compute units. The compute units include multiple lanes of execution. Due to a variety of types of manufacturing defects, one or more of the partitions of the processing unit has less than a predetermined number of operational compute units. To balance the throughput of the multiple partitions, a power manager generates both static and dynamic scaling factors based on at least the corresponding number of operational compute units. Using these scaling factors, the power manager adjusts the operation parameters of power domains for the partitions relative to one another.

Abstract: Platform power management includes boosting performance in a platform power boost mode or restricting performance to keep a power or temperature under a desired threshold in a platform power cap mode. Platform power management exploits the mutually exclusive nature of activities and the associated headroom created in a temperature and/or power budget of a server platform to boost performance of a particular component while also keeping temperature and/or power below a threshold or budget.

Abstract: Platform power management includes boosting performance in a platform power boost mode or restricting performance to keep a power or temperature under a desired threshold in a platform power cap mode. Platform power management exploits the mutually exclusive nature of activities and the associated headroom created in a temperature and/or power budget of a server platform to boost performance of a particular component while also keeping temperature and/or power below a threshold or budget.

Abstract: A chip for multi-die communications couplings using a single bridge die, includes: a plurality of dies each including one or more functional circuit blocks; and a first bridge die directly communicatively coupling two or more pairs of dies of the plurality of dies.

Abstract: Platform power management includes boosting performance in a platform power boost mode or restricting performance to keep a power or temperature under a desired threshold in a platform power cap mode. Platform power management exploits the mutually exclusive nature of activities and the associated headroom created in a temperature and/or power budget of a server platform to boost performance of a particular component while also keeping temperature and/or power below a threshold or budget.

Abstract: Platform power management includes boosting performance in a platform power boost mode or restricting performance to keep a power or temperature under a desired threshold in a platform power cap mode. Platform power management exploits the mutually exclusive nature of activities and the associated headroom created in a temperature and/or power budget of a server platform to boost performance of a particular component while also keeping temperature and/or power below a threshold or budget.

Abstract: Platform power management includes boosting performance in a platform power boost mode or restricting performance to keep a power or temperature under a desired threshold in a platform power cap mode. Platform power management exploits the mutually exclusive nature of activities and the associated headroom created in a temperature and/or power budget of a server platform to boost performance of a particular component while also keeping temperature and/or power below a threshold or budget.

Abstract: A processing system includes one or more power supply monitors (PSMs) to measure one or more first voltages corresponding to one or more locations in the processing system. The measurements are performed concurrently with the processing system executing one or more code loops. The processing system also includes calibration logic to modify a second voltage provided to the processing system based on a comparison of a reference voltage and the one or more first voltages. The reference voltage is determined based on previous execution of the one or more code loops by the processing system.

Abstract: A method for automatically scaling estimates of digital power consumed by a portion of an integrated circuit (IC) device by the operating frequency of the portion of the IC are described herein. The method may include obtaining an energy value which may correspond to an amount of energy used by the portion of the IC. A cumulative energy value may be generated by repeatedly, at a frequency proportional to the operating frequency of the portion of the IC, obtaining energy values and adding each obtained energy value to a sum of energy values for the portion of the IC. The cumulative energy value may be sampled at a time sample interval to generate an estimate of the portion of the IC's digital power consumption that is automatically scaled with the operating frequency of the portion of the IC.

Abstract: A method and apparatus using temperature margin to balance performance with power allocation. Nominal, middle and high power levels are determined for compute elements. A set of temperature thresholds are determined that drive the power allocation of the compute elements towards a balanced temperature profile. For a given workload, temperature differentials are determined for each of the compute elements relative the other compute elements, where the temperature differentials correspond to workload utilization of the compute element. If temperature overhead is available, and a compute element is below a temperature threshold, then particular compute elements are allocated power to match or drive toward the balanced temperature profile.

Abstract: A system and method for efficient management of operating modes within an integrated circuit (IC) for optimal power and performance targets. A semiconductor chip includes one or more processing units each of which operates with respective operating parameters. One or more temperature sensors are included to measure a temperature of the one or more processing units during operation. When the measured temperature exceeds a threshold, a power manager on the chip determines a temperature headroom utilizing temperature values based on worst-case ambient temperature. When the measured temperature does not exceed the threshold, the power manager determines the temperature headroom utilizing at least one temperature value based on room ambient temperature. Following, the power manager adjusts the respective operating parameters based on at least the temperature headroom.

Abstract: A processor employs a set of replica paths at a processor to determine an operating frequency and voltage for the processor. The replica paths each represent one or more circuit paths at a functional module of the processor. The delays at the replica paths are normalized to increase the likelihood that the replica paths accurately represent the behavior of the circuit paths of the functional module. After normalization, a distribution of delay values is generated by varying, at each replica path, the delay at an output node of the replica path until a mismatch is detected between a signal at the output node of the replica path and the delayed representation of the signal. The resulting distribution of delay values can then be adjusted based on variations in reference voltages at the replica paths to account for potential distribution errors resulting from the reference voltage variations.

Abstract: A processor employs a set of replica paths at a processor to determine an operating frequency and voltage for the processor. The replica paths each represent one or more circuit paths at a functional module of the processor. The delays at the replica paths are normalized to increase the likelihood that the replica paths accurately represent the behavior of the circuit paths of the functional module. After normalization, a distribution of delay values is generated by varying, at each replica path, the delay at an output node of the replica path until a mismatch is detected between a signal at the output node of the replica path and the delayed representation of the signal. The resulting distribution of delay values can then be adjusted based on variations in reference voltages at the replica paths to account for potential distribution errors resulting from the reference voltage variations.

Abstract: A processing system includes one or more power supply monitors (PSMs) to measure one or more first voltages corresponding to one or more locations in the processing system. The measurements are performed concurrently with the processing system executing one or more code loops. The processing system also includes calibration logic to modify a second voltage provided to the processing system based on a comparison of a reference voltage and the one or more first voltages. The reference voltage is determined based on previous execution of the one or more code loops by the processing system.

Abstract: A system and method for efficient management of operating modes within an integrated circuit (IC) for optimal power and performance targets. A semiconductor chip includes one or more processing units each of which operates with respective operating parameters. One or more temperature sensors are included to measure a temperature of the one or more processing units during operation. When the measured temperature exceeds a threshold, a power manager on the chip determines a temperature headroom utilizing temperature values based on worst-case ambient temperature. When the measured temperature does not exceed the threshold, the power manager determines the temperature headroom utilizing at least one temperature value based on room ambient temperature. Following, the power manager adjusts the respective operating parameters based on at least the temperature headroom.

Abstract: A method and apparatus for load step, or instantaneous current spike, mitigation are provided. In the method and apparatus, load steps are mitigated if a computer system a whole is lightly load, which may be determined by the power consumption of the computer system. Further, load steps are mitigated if a number of processor cores capable of inducing a load step is higher than a threshold. The Advanced Configuration and Power Interface (ACPI) performance state of the cores is used to determine a core's potential for generating a load step. A processor core is instructed to mitigate load steps if conditions are met for the mitigation.

Abstract: A method for automatically scaling estimates of digital power consumed by a portion of an integrated circuit (IC) device by the operating frequency of the portion of the IC are described herein. The method may include obtaining an energy value which may correspond to an amount of energy used by the portion of the IC. A cumulative energy value may be generated by repeatedly, at a frequency proportional to the operating frequency of the portion of the IC, obtaining energy values and adding each obtained energy value to a sum of energy values for the portion of the IC. The cumulative energy value may be sampled at a time sample interval to generate an estimate of the portion of the IC's digital power consumption that is automatically scaled with the operating frequency of the portion of the IC.

Abstract: A method and apparatus using temperature margin to balance performance with power allocation. Nominal, middle and high power levels are determined for compute elements. A set of temperature thresholds are determined that drive the power allocation of the compute elements towards a balanced temperature profile. For a given workload, temperature differentials are determined for each of the compute elements relative the other compute elements, where the temperature differentials correspond to workload utilization of the compute element. If temperature overhead is available, and a compute element is below a temperature threshold, then particular compute elements are allocated power to match or drive toward the balanced temperature profile.

Abstract: The operating point of a processing unit is controlled based on the power consumption (i.e., the rate of energy consumption) associated with a workload, wherein low power consumption may indicate short-duration workloads with idle phases and high power consumption may indicate long, sustained workloads. Energy credits are accumulated while a drain rate of a battery is lower than a threshold drain rate and the energy credits are consumed while the drain rate is higher than the threshold drain rate. The operating point of the processing unit may be increased from a first operating point to a second operating point in response to the energy credits exceeding a first threshold. The operating point of the processing unit may be decreased from the second operating point to the first operating point in response to the energy credits falling below a second threshold.

Abstract: A method for automatically scaling estimates of digital power consumed by a portion of an integrated circuit (IC) device by the operating frequency of the portion of the IC are described herein. The method may include obtaining an energy value which may correspond to an amount of energy used by the portion of the IC. A cumulative energy value may be generated by repeatedly, at a frequency proportional to the operating frequency of the portion of the IC, obtaining energy values and adding each obtained energy value to a sum of energy values for the portion of the IC. The cumulative energy value may be sampled at a time sample interval to generate an estimate of the portion of the IC's digital power consumption that is automatically scaled with the operating frequency of the portion of the IC.