Abstract: A method includes controlling a power limit of a computing system based on a determined skin temperature of at least one location on an outer surface of a device housing the computing system. A processor includes a processing unit and a power management controller to control a power limit of the processing unit based on a determined skin temperature of at least one location on an outer surface of a device housing the processor.

Abstract: A method includes adjusting a maximum skin temperature threshold of a device based on a device state, adjusting a power limit for the device based on the adjusted maximum skin temperature threshold, and operating the device based on the adjusted power limit. A processor includes a processing unit and a power management controller to adjust a maximum skin temperature threshold based on a device state and adjust a power limit for the processing unit based on the adjusted maximum skin temperature threshold.

Abstract: A method includes controlling a power limit of a computing system based on a determined skin temperature of at least one location on an outer surface of a device housing the computing system. A processor includes a processing unit and a power management controller to control a power limit of the processing unit based on a determined skin temperature of at least one location on an outer surface of a device housing the processor.

Abstract: Systems, methodologies, media, and other embodiments associated with detecting and responding to a degradation of a direct current provided to a frequency scalable processor are described. One exemplary frequency scalable processor includes a voltage regulating logic configured to request that a direct current having a reference voltage be provided to the processor. The example processor may also include a logic for detecting whether the voltage matches the reference voltage to within a desired tolerance and to selectively store processor state and/or data based on the detecting.

Abstract: Systems, methodologies, media, and other embodiments associated with making a frequency change through frequency synthesis and digital selection of out-of-phase synthesized signals are described. One exemplary system embodiment includes a locked loop logic (e.g., phase locked, delay locked) that may receive a reference clock signal, process the reference clock signal into signals with different phases, and make those signals available to a selection logic. The exemplary system may also include a state logic that stores frequency divisors that facilitate selecting and tracking output signals provided by the selection logic. The exemplary system may also include a phase logic that stores output signal phase data associated with computing, describing, and/or selecting an output signal.

Abstract: A processing system including a plurality of processors, a cache data array, and a crossbar interface connecting the processors with the cache data array. Each processor includes a tag array mapped to the cache data array. In another embodiment, the cache data array includes a plurality of sub-arrays accessible via a plurality of ports of the crossbar interface. The system allows an upper-level cache data array to be shared among processors while cache latency is reduced.

Abstract: A processing system includes a cache controller for managing requests for data from a cache memory by a processor. The cache controller includes an access queue that holds requests for data pending asynchronous retrieval of the requested data from the cache memory, and an exit queue that holds the requested data retrieved from the cache memory until released to the processor. This queuing arrangement allows data lines to be retrieved from cache memory without a pipeline, while latencies are minimized.

Abstract: A processing system crossbar includes control sub-ports and mini-ports selectively configurable as connection points. Each control sub-port has a domain of mini-ports that the control sub-port is configured to selectively control. Each mini-port is configurable to select a control sub-port from those having domains that include the selecting mini-port. Each connection point includes a corresponding control sub-port and each mini-port selecting the corresponding control sub-port. The crossbar provides bandwidth tailored for various system agents. Thus crossbar bottlenecks are eliminated or reduced.

Abstract: A processing system including a plurality of processors, a cache data array, and a crossbar interface connecting the processors with the cache data array. Each processor includes a tag array mapped to the cache data array. In another embodiment, the cache data array includes a plurality of sub-arrays accessible via a plurality of ports of the crossbar interface. The system allows an upper-level cache data array to be shared among processors while cache latency is reduced.

Abstract: A processing system crossbar includes control sub-ports and mini-ports selectively configurable as connection points. Each control sub-port has a domain of mini-ports that the control sub-port is configured to selectively control. Each mini-port is configurable to select a control sub-port from those having domains that include the selecting mini-port. Each connection point includes a corresponding control sub-port and each mini-port selecting the corresponding control sub-port. The crossbar provides bandwidth tailored for various system agents. Thus crossbar bottlenecks are eliminated or reduced.

Abstract: The present invention is directed to a method for evaluating a circuit design to identify potential race conditions including the steps of identifying switching elements in a design, storing control node and switched node pair information for each of the switching elements, identifying stacks of the switching elements; storing information about the stacks of switching elements; identifying parallel connected ones of the switching elements; identifying parallel stacks; and calculating a combined switching current for the parallel switching elements and stacks.

Abstract: The present invention is directed to a method for evaluating a circuit design to identify potential race conditions including the steps of identifying switching elements in a design, storing control node and switched node pair information for each of the switching elements, identifying stacks of the switching elements; storing information about the stacks of switching elements; identifying parallel connected ones of the switching elements; identifying parallel stacks; and calculating a combined switching current for the parallel switching elements and stacks.

Abstract: A processing system includes a cache controller for managing requests for data from a cache memory by a processor. The cache controller includes an access queue that holds requests for data pending asynchronous retrieval of the requested data from the cache memory, and an exit queue that holds the requested data retrieved from the cache memory until released to the processor. This queuing arrangement allows data lines to be retrieved from cache memory without a pipeline, while latencies are minimized.

Abstract: A system for recovering most recent writer status when a mispredicted branch occurs in a processor that executes instructions out of order. A queue holds instructions stored in the order they are fetched from memory. Each slot in the queue stores a target register that will receive the results of the instruction, and a most recent writer status bit indicating whether the slot is the last instruction to write to the target register. When inserting a new instruction, each slot compares the target register of the new instruction to its target register, and when a match occurs, the slot resets its most recent writer status, and stores the new instruction slot number as a target taker. When a mispredicted branch occurs, the slot compares the mispredicted branch slot to the target taker slot, and when the target taker slot is greater, the slot regains the most recent writer status.