Abstract: A circuit and method has a processing unit, a master clock generator for providing a master clock and a plurality of phase-locked loops, each providing a respective clock signal. A plurality of dynamically variable delay circuits each has a plurality of predetermined delay amounts. Clocked circuits are coupled to respective clock signals provided by respective phase-locked loops. A performance detector is coupled to receive the clock signals for determining a center of a quiet zone for at least one of the plurality of phase-locked loops. The phase-locked loops are turned off and on and a respective one of the plurality of dynamically variable delay circuits is set to have a new predetermined value of delay which adjusts an edge of the master clock to a location that permits the data processing system to operate near substantially the center of the quiet zone.

Abstract: A circuit and method has a processing unit, a master clock generator for providing a master clock and a plurality of phase-locked loops, each providing a respective clock signal. A plurality of dynamically variable delay circuits each has a plurality of predetermined delay amounts. Clocked circuits are coupled to respective clock signals provided by respective phase-locked loops. A performance detector is coupled to receive the clock signals for determining a center of a quiet zone for at least one of the plurality of phase-locked loops. The phase-locked loops are turned off and on and a respective one of the plurality of dynamically variable delay circuits is set to have a new predetermined value of delay which adjusts an edge of the master clock to a location that permits the data processing system to operate near substantially the center of the quiet zone.

Abstract: A receive test accelerator retrieves an adjusted jitter amount and an adjusted test time in which to test a device. The adjusted jitter amount and the adjusted test time correspond to an adjusted bit error rate that is extrapolated from a baseline bit error rate, which corresponds to a baseline jitter amount. In turn, the receive test accelerator tests the device, at the adjusted test time, using a data stream that is modulated by the adjusted jitter amount.

Abstract: A receive test accelerator retrieves an adjusted jitter amount and an adjusted test time in which to test a device. The adjusted jitter amount and the adjusted test time correspond to an adjusted bit error rate that is extrapolated from a baseline bit error rate, which corresponds to a baseline jitter amount. In turn, the receive test accelerator tests the device, at the adjusted test time, using a data stream that is modulated by the adjusted jitter amount.

Abstract: A test apparatus and device under test has a probe that can be located very close to contact pads and that requires very few solder connections. In addition, the probe can be configured to meet any appropriate and desired electrical specification while still using a same circuit board. There is no need to attach discrete components to a circuit board. Thus, by using a configurable probe, a single circuit board may be used with multiple probes or a reconfigurable probe to test for compliance with a variety of different electrical specifications having different requirements.

Abstract: A test apparatus and device under test has a probe that can be located very close to contact pads and that requires very few solder connections. In addition, the probe can be configured to meet any appropriate and desired electrical specification while still using a same circuit board. There is no need to attach discrete components to a circuit board. Thus, by using a configurable probe, a single circuit board may be used with multiple probes or a reconfigurable probe to test for compliance with a variety of different electrical specifications having different requirements.