Abstract: Systems and methods of edge calibration for synchronous data transfer between clock domains are disclosed. An exemplary method may comprise comparing a drive clock signal to a receive clock signal, generating a select clock signal, and configuring a data path based a least in part on the select clock signal for synchronous data transfer between clock domains so that data arrives in an early clock domain at the desired logical clock cycle.

Abstract: Systems and methods for implanting synchronous data transfer between clock domains are disclosed. An exemplary system may comprise an adaptable data path having an input for receiving a signal from a first clock domain and an output in a second clock domain. A controller is operatively associated with the adaptable data path. The controller is responsive to operating parameters to configure the adaptable data path to align a logical clock pulse on the signal received from the first clock domain with the same logical clock pulse in the second clock domain based on a measured delay between the first and second clock domains.

Abstract: Techniques are disclosed for increasing reliability of an integrated circuit. In one embodiment, an integrated circuit includes core chip circuitry. The integrated circuit includes means for increasing a power supply voltage V provided to the core chip circuitry, such as by increasing the voltage V to a maximum value. The integrated circuit also includes means for identifying a clock frequency F for which F<Pmax/(CV2), where C is a switching capacitance and where Pmax is a predetermined maximum power consumption of the core chip circuitry. The integrated circuit also includes means for providing a clock signal having frequency F to the circuit.

Abstract: Systems and methods for implementing count calibration for synchronous data transfer between clock domains are disclosed. An exemplary system may include a count calibration circuit for determining latency between an early clock domain and a late clock domain. The system may also include a data path configurable for synchronous data transfer between clock domains based at least in part on the latency.

Abstract: For one disclosed embodiment, a supply voltage regulator is to control voltage at a first supply node for a circuit. The supply voltage regulator includes one or more first devices to couple the first supply node to a second supply node when the circuit is in a predetermined operational state and includes an error sensor to control the one or more first devices. The supply voltage regulator includes one or more second devices to couple the first supply node to a third supply node when the circuit is in the predetermined operational state. Other embodiments are also disclosed.

Abstract: A method of generating a clock signal using a digital frequency synthesizer includes providing a base clock to the digital frequency synthesizer, comparing a phase of an output clock from the digital frequency synthesizer with a phase of a reference signal, and issuing at least one frequency control command to the digital frequency synthesizer to align the phases.

Abstract: Systems and methods for error recovery in an integer execution unit of a multi-core processor are disclosed. In an exemplary embodiment a method may comprise checking parity for a transaction in an execution data path having parallel data registers. The method may also comprise copying one of the parallel data registers to a corrupt data register if parity fails.

Abstract: In a preferred embodiment, the invention provides a circuit and method for reducing soft error events in latches. A low-pass filter is placed between the output of a forward inverter and the inputs of a feedback keeper. The first and second outputs of the low-pass filter are connected to first and second inputs respectively of the feedback keeper. The only type of diffusion connected to the first output of the low-pass filter is a P-type diffusion. The only type of diffusion connected to the second output of the low-pass filter is an N-type diffusion. The feedback keeper is connected to an input of the forward inverter.

Abstract: A thermal sensing system may comprise a plurality of remote sensors distributed across an integrated circuit (IC). Each of the plurality of remote sensors provides an analog signal that varies as a function of temperature of a respective region of the IC where each respective remote sensor is located. A central system, forming part of the IC, samples the analog signals from the plurality of remote sensors and converts the sampled analog signals to corresponding digital values.

Abstract: Systems and methods for implementing count calibration for synchronous data transfer between clock domains are disclosed. An exemplary system may include a count calibration circuit for determining latency between an early clock domain and a late clock domain. The system may also include a data path configurable for synchronous data transfer between clock domains based at least in part on the latency.

Abstract: Systems and methods for implanting synchronous data transfer between clock domains are disclosed. An exemplary system may comprise an adaptable data path having an input for receiving a signal from a first clock domain and an output in a second clock domain. A controller is operatively associated with the adaptable data path.

Abstract: Systems and methods of edge calibration for synchronous data transfer between clock domains are disclosed. An exemplary method may comprise comparing a drive clock signal to a receive clock signal, generating a select clock signal, and configuring a data path based a least in part on the select clock signal for synchronous data transfer between clock domains so that data arrives in an early clock domain at the desired logical clock cycle.

Abstract: Systems and methods for maintaining performance of an integrated circuit are disclosed. One embodiment of a system may comprise a working power limit evaluator that determines a working power limit as a function of at least one performance factor associated with variations that affect performance of the integrated circuit. The system may further comprise a power management system that varies power of the integrated circuit based on the working power limit and an actual power of the integrated circuit to maintain a substantially constant performance.

Abstract: In one embodiment, a central processing unit (CPU) includes multiple clock zones. Each clock zone includes at least one sensor that generates a signal indicative of a power supply voltage within the clock zone, a clock generator for providing a variable frequency clock to the clock zone, a first controller for controlling a frequency of operation of the clock generator in response to the at least one sensor, wherein the first controller further controls the frequency of operation in response to communication of frequency adjustments from first controllers in other clock zones within one cycle of latency, and a second controller that provides an overdrive signal, that is combined with adjustment signals from the first controller for the clock generator, in response to communication of frequency adjustments from other clock zones beyond one cycle of latency.

Abstract: A computer processor integrated circuit has multiple functional units, where each unit is coupled to a register file for reading and writing operands. An instruction fetch unit receives instructions from a memory system and dispatches commands to the functional units. The processor has a resource status flags register wherein particular units may be marked enabled or disabled. The instruction fetch and decode unit checks the resource status flags register prior to dispatching commands and dispatches commands only to those functional units marked enabled. The instruction fetch and decode unit is capable of dispatching commands to available units, and of stalling and dispatching remaining commands in a following cycle if insufficient resources are available to simultaneously dispatch all commands necessary to execute an instruction or group of instructions.

Abstract: A system and a method of providing error detection and correction of transmission of multiple flits between sending and receiving agents connected together in a network or computer interconnect environment is disclosed that comprises embedding a sequence identifier in each flit prior to transmission, sending each flit to a connected receiving agent, examining the sequence identifiers of each flit being received and requesting the sending agent to resend a flit if the sequence identifier for that flit is determined to be incorrect. In a preferred embodiment of the present invention, the sequence identifier is embedded in the control portion of the flit and comprises a sequence number that is incremented or otherwise changed in a predictable manner, so that the order of flits being received is predicted. If the sequence number for a flit is different that expected, the receiving agent requests that it be resent.

Abstract: One disclosed embodiment may comprise an interpolation system that includes an interpolator that interpolates between a selected phase from a preceding cycle and a selected phase from a current cycle to provide an interpolated phase for the current cycle. An edge of the interpolated phase for the current cycle has reduced jitter relative to an edge of a corresponding phase of the current cycle. A delay system delays a plurality of other phases of the current cycle to provide delayed other phases, the delayed other phases and the interpolated phase for the current cycle collectively defining a set of adjusted phases for the current cycle.

Abstract: A processor integrated circuit has at least one processor and two or more levels of cache memory. A first power connection provides power to the processor and lower level cache, which form a first power domain. The integrated circuit has a second power connection providing power to upper level cache of the circuit, forming a second power domain. There may be additional power connections to the integrated circuit, forming additional power domains, such as periphery or memory-interface power.

Abstract: Systems, methodologies, media, and other embodiments associated with detecting and responding to a degradation of a direct current provided to a frequency scalable processor are described. One exemplary frequency scalable processor includes a voltage regulating logic configured to request that a direct current having a reference voltage be provided to the processor. The example processor may also include a logic for detecting whether the voltage matches the reference voltage to within a desired tolerance and to selectively store processor state and/or data based on the detecting.

Abstract: Systems, methodologies, media, and other embodiments associated with making a frequency change through frequency synthesis and digital selection of out-of-phase synthesized signals are described. One exemplary system embodiment includes a locked loop logic (e.g., phase locked, delay locked) that may receive a reference clock signal, process the reference clock signal into signals with different phases, and make those signals available to a selection logic. The exemplary system may also include a state logic that stores frequency divisors that facilitate selecting and tracking output signals provided by the selection logic. The exemplary system may also include a phase logic that stores output signal phase data associated with computing, describing, and/or selecting an output signal.